| No. | Partie # | Fabricant | Description | Fiche Technique |
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Central Semiconductor |
ULTRA LOW LEAKAGE SWITCHING DIODE VR=0, f=1.0MHz 2.0 trr IR=IF=10mA, Irr=1.0mA, RL=100Ω 3.0 UNITS V V mA A A mW °C °C/W UNITS pA V V V V pF μs R6 (15-June 2015) CMLD6001 SURFACE MOUNT SILICON DUAL, ISOLATED ULTRA LOW LEAKAGE SWITCHING DIODE SOT-563 CASE - MECHANICAL OUTLINE |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
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ON Semiconductor |
Power MOSFET current limiting for short circuit protection, integrated Gate−Source clamping for ESD protection and integral Gate−Drain clamping for over−voltage protection and technology for low on−resistance. No additional gate series resistance is required when |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL PAIR HIGH VOLTAGE SCHOTTKY DIODES • High Voltage (70V) • Low Forward Voltage • Various Dual Pair Configurations MAXIMUM RATINGS: (TA=25°C) Peak Repetitive Reverse Voltage Continuous Forward Current Peak Forward Surge Current, tp=1.0s Power Dissipation Operating and Storage Junction |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL PAIR HIGH VOLTAGE SCHOTTKY DIODES • High Voltage (70V) • Low Forward Voltage • Various Dual Pair Configurations MAXIMUM RATINGS: (TA=25°C) Peak Repetitive Reverse Voltage Continuous Forward Current Peak Forward Surge Current, tp=1.0s Power Dissipation Operating and Storage Junction |
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Central Semiconductor |
Dual-Channel MOSFET • ESD protection up to 1800V (Human Body Model) • 350mW power dissipation • Very low rDS(ON) • Low threshold voltage • Logic level compatible • Small, SOT-563 surface mount package MAXIMUM RATINGS: (TA=25°C) Drain-Source Voltage Gate-Source Voltage |
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Central Semiconductor |
SILICON DUAL N-CHANNEL MOSFETS D IS IDM ISM PD PD PD TJ, Tstg ΘJA 60 60 40 280 280 1.5 1.5 350 300 150 -65 to +150 357 UNITS V V V mA mA A A mW mW mW °C °C/W ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX IGSSF, I |
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Central Semiconductor |
SILICON DUAL N-CHANNEL MOSFETS D IS IDM ISM PD PD PD TJ, Tstg ΘJA 60 60 40 280 280 1.5 1.5 350 300 150 -65 to +150 357 UNITS V V V mA mA A A mW mW mW °C °C/W ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX IGSSF, I |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
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Central Semiconductor |
SURFACE MOUNT SILICON DUAL / HIGH VOLTAGE SWITCHING DIODES |
|
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ON Semiconductor |
Power MOSFET current limiting for short circuit protection, integrated Gate−Source clamping for ESD protection and integral Gate−Drain clamping for over−voltage protection and technology for low on−resistance. No additional gate series resistance is required when |
|
|
|
|
Central Semiconductor |
SURFACE MOUNT SILICON DUAL PAIR HIGH VOLTAGE SCHOTTKY DIODES • High Voltage (70V) • Low Forward Voltage • Various Dual Pair Configurations MAXIMUM RATINGS: (TA=25°C) Peak Repetitive Reverse Voltage Continuous Forward Current Peak Forward Surge Current, tp=1.0s Power Dissipation Operating and Storage Junction |
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Central Semiconductor |
SILICON DUAL N-CHANNEL MOSFETS D IS IDM ISM PD PD PD TJ, Tstg ΘJA 60 60 40 280 280 1.5 1.5 350 300 150 -65 to +150 357 UNITS V V V mA mA A A mW mW mW °C °C/W ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (TA=25°C unless otherwise noted) SYMBOL TEST CONDITIONS MIN MAX IGSSF, I |
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