| No. | Partie # | Fabricant | Description | Fiche Technique |
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Hitachi Semiconductor |
These devices each consist of four 2-input digital multiplexers with common select and strobe inputs • • • • • High Speed Operation: tpd (Data to Output) = 12 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = |
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ON Semiconductor |
Hex Schmitt-Trigger Inverter • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance With the JEDEC Stand |
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National Semiconductor |
8-3 Line Priority Encoder Y Typical propagation delay 13 ns Y Wide supply voltage range 2V – 6V Connection Diagram Dual-In-Line Package Truth Table Order Number MM54HC148 or MM74HC148 TL F 9390 – 1 Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HXXXXXXXX H H H H H |
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IK Semiconductor |
Triple 3-Input AND Gate ply Current, VCC and GND Pins Power Dissipation in Still Air, Plastic DIP+ SOIC Package+ Storage Temperature Lead Temperature, 1 mm from Case for 10 Seconds (Plastic DIP or SOIC Package) Value -0.5 to +7.0 -1.5 to VCC +1.5 -0.5 to VCC +0.5 ±20 ±25 ± |
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ON Semiconductor |
8-Bit Serial or Parallel-Input/Serial-Output Shift Register • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS, and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance with the Requirements |
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Fairchild Semiconductor |
Hex Schmitt Inverter • High Speed: tPD = 5.5 ns (Typ.) at VCC = 5 V • Low Power Dissipation: ICC = 2 μA (Max.) at TA = 25°C • High Noise Immunity: VNIH = VNIL = 28% VCC (Min.) • Power down protection is provided on all inputs • Low Noise: VOLP = 0.8 V (Max.) • Pin and Fu |
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IK Semiconductor |
8-Bit Parallel-in Serial-Out Shift Register either of the clock inputs are held high, holding either input low enables the other clock input. This will allow the system clock to be free running and the register stopped on command with the other clock input. A change from low-to-high on the clo |
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Hitachi Semiconductor |
Inverter with Schmitt-trigger Input • The basic gate function is lined up as hitachi uni logic series. • Supplied on emboss taping for high speed automatic mounting. • Electrical characteristics equivalent to the HD74HC14 Supply voltage range : 2 to 6 V Operating temperature range : –4 |
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National Semiconductor |
Synchronous Binary Up/Down Counters Y Level changes on Enable or Down Up can be made regardless of the level of the clock input Y Wide power supply range 2 – 6V Y Low quiescent supply current 80 mA maximum (74HC Series) Y Low input current 1 mA maximum Connection Diagram Dual-In-Line |
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ON Semiconductor |
Hex Schmitt-Trigger Inverter • Output Drive Capability: 10 LSTTL Loads • Outputs Directly Interface to CMOS, NMOS and TTL • Operating Voltage Range: 2.0 to 6.0 V • Low Input Current: 1.0 mA • High Noise Immunity Characteristic of CMOS Devices • In Compliance With the JEDEC Stand |
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Motorola Semiconductor |
8-Input Data Selector / Multiplexer |
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IK Semiconductor |
Dual 2-4 Decoder/Demultiplexer L H L H Y0 H L H H H Outputs Y1 H H L H H Y2 H H H L H Y3 H H H H L w w w .d h s a t a ee . u t4 m o c X = don’t care 1 www.DataSheet4U.com IN74HC139A MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply V |
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Hitachi Semiconductor |
2-input Exclusive-OR Gate • The basic gate function is lined up as hitachi uni logic series. • Supplied on emboss taping for high speed automatic mounting. • Electrical characteristics equivalent to the HD74HC86 Supply voltage range : 2 to 6 V Operating temperature range : –4 |
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ON Semiconductor |
Single Non-Inverting Buffer • Designed for 2.0 V to 5.5 V VCC Operation • 3.5 ns tPD at 5 V (typ) • Inputs/Outputs Over−Voltage Tolerant up to 5.5 V • IOFF Supports Partial Power Down Protection • Source/Sink 8 mA at 3.0 V • Available in SC−88A and TSOP−5 Packages • Chip Comple |
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Hitachi Semiconductor |
Dual Retriggerable Monostable Multivibrators both a negative, A, and a positive, B, transition triggered input, either of which can be used as an inhibit input. Also included is a clear input that when taken low resets the one shot. The HD74HC123A can be triggered on the positive transition of |
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Hitachi Semiconductor |
Synchronous Decade/4-bit Binary/Counter(Direct Clear/Synchronous Clear) • • • • High Speed Operation: tpd (Clock to Q) = 18 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max HD74HC160/HD74HC161/HD74HC162/HD74HC163 • Low Quiescent Supply C |
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Hitachi Semiconductor |
4-bit D-type Register • • • • • High Speed Operation: tpd (Clock to Q) = 14 ns typ (CL = 50 pF) High Output Current: Fanout of 10 LSTTL Loads Wide Operating Voltage: VCC = 2 to 6 V Low Input Current: 1 µA max Low Quiescent Supply Current: ICC (static) = 4 µA max (Ta = 25° |
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Hitachi Semiconductor |
4-bit Parallel-Access Shift Register parallel inputs, parallel outputs, J-K serial inputs, Shift/Load control input, and a direct overriding clear. This shift register can operate in two modes: Parallel load; shift from QA towards QD. Paralle loading is accomplished by applying the four |
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National Semiconductor |
8-3 Line Priority Encoder Y Typical propagation delay 13 ns Y Wide supply voltage range 2V – 6V Connection Diagram Dual-In-Line Package Truth Table Order Number MM54HC148 or MM74HC148 TL F 9390 – 1 Inputs Outputs EI 0 1 2 3 4 5 6 7 A2 A1 A0 GS EO HXXXXXXXX H H H H H |
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National Semiconductor |
Synchronous Binary Up/Down Counters Y Level changes on Enable or Down Up can be made regardless of the level of the clock input Y Wide power supply range 2 – 6V Y Low quiescent supply current 80 mA maximum (74HC Series) Y Low input current 1 mA maximum Connection Diagram Dual-In-Line |
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