| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
National Semiconductor |
BCD-to-Decimal Decoder Y Supply voltage range Y Tenth power TTL compatible 3V to 15V drive 2 LPTTL loads Y High noise immunity Y Low power Y Medium speed operation 0 45 VCC (typ ) 50 nW (typ ) 10 MHz (typ ) with 10V VCC Applications Y Automotive Y Data terminals Y Inst |
|
|
|
|
National Semiconductor |
Decade Counter with Asynchronous Clear |
|
|
|
|
National Semiconductor |
Parallel-Load 8-Bit Shift Register Y Wide supply voltage range Y Guaranteed noise margin Y High noise immunity Y Low power TT |
|
|
|
|
National Semiconductor |
(MM74C160 - MM74C163) Decade Counter with Asynchronous Clear |
|
|
|
|
National Semiconductor |
BCD-to-7 Segment Latch/Decoder/Driver Y Typical propagation delay 60 ns Y Supply voltage range 2 – 6V Y Maximum input current 1 mA Y Maximum quiescent supply current 80 mA (74HC) Y Display blanking Y Low dynamic power consumption Connection Diagram Dual-In-Line Package Top View TL F 5 |
|
|
|
|
National Semiconductor |
MM74C910 Y Supply voltage range Y High noise immunity Y TTL compatible fan out Y Input address register Y Low power consumption Y Fast access time Y TRI-STATE outputs Y High voltage inputs 3 0V to 5 5V 0 45VCC (typ ) 1 TTL load 250 nW package (typ ) (chip en |
|
|
|
|
National Semiconductor |
MM74C912 |
|
|
|
|
National Semiconductor |
AND-OR-Invert Gate Y Typical propagation delay 10 ns Y Wide power supply range 2 – 6V Y Low quiescent supply current 20 mA maximum (74 Series) Y Low input current 1 mA maximum Y High output current 4 mA minimum Connection Diagrams Dual-In-Line Package Top View Order |
|
|
|
|
National Semiconductor |
Hex D Flip-Flops Y Typical propagation delay 16 ns Y Wide operating voltage range 2 – 6V Y Low input current |
|
|
|
|
National Semiconductor |
Octal D-Type Flip-FLop |
|
|
|
|
National Semiconductor |
8-Bit Magnitude Comparator Y TTL input compatible Y Typical propagation delay 20 ns Y Low quiescent current 80 mA maximum (74HCT Series) Y Large output current 4 mA Y Same as HCT521 Logic Diagrams C1995 National Semiconductor Corporation TL F 5371 TL F 5371 – 2 RRD-B30M105 |
|
|
|
|
National Semiconductor |
MM74C915 |
|
|
|
|
National Semiconductor |
7-Segment-to-BCD Converter |
|
|
|
|
National Semiconductor |
8-Input NAND Gate |
|
|
|
|
National Semiconductor |
4-Bit Decade Counter Y Wide supply voltage range Y Guaranteed noise margin |
|
|
|
|
National Semiconductor |
Phase Comparator Y Y Y Y Wide supply voltage range Convenient mini-DIP package TRI-STATE phase-comparator output (comparator II) 200 mV input voltage (signal in) sensitivity (typical) Block and Connection Diagrams www.DataSheet4U.com TL F 5921 – 1 Dual-In-Line Pac |
|
|
|
|
National Semiconductor |
256 Bit Tri-state Random Access Read/write Memory Y Y Y Y Y Supply voltage range High noise immunity TTL compatible fan out Input address register Low power consumption Fast access time TRI-STATE outputs High voltage inputs 3 0V to 5 5V 0 45VCC (typ ) 1 TTL load 250 nW package (typ ) (chip enabled |
|
|
|
|
National Semiconductor |
Dual Retriggerable Monostable Multivibrator both a negative A and a positive B transition triggered input either of which can be used as an inhibit input Also included is a clear input that when taken low resets the one shot The ’HC123 can be triggered on the positive transition of the clear w |
|
|
|
|
National Semiconductor |
12-Bit Successive Approximation Register Y Wide supply voltage range 3 0V to15V Y Guaranteed noise margin 1 0V Y High noise immunity Y Low power TTL 0 45VCC typ fan out of 2 compatibility driving 74L Y Provision for register extension or truncation Y Operates in START STOP or cont |
|
|
|
|
National Semiconductor |
Quad 2-Input OR Gate Y Wide supply voltage range Y Guaranteed noise margin Y High noise immunity Y Low power TTL compatibility Connection Diagram Dual-In-Line Package February 1988 3 0V to 15V 1 0V 0 45V VCC (typ ) fan out of 2 driving 74L Top View Order Number MM54C |
|