No. | Partie # | Fabricant | Description | Fiche Technique |
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National Semiconductor |
Series Monolithic JFET Input Operational Amplifiers n Low input bias current: 30pA n Low Input Offset Current: 3pA n High input impedance: 1012Ω n Low input noise current: n High common-mode rejection ratio: n Large dc voltage gain: 106 dB 100 dB Features Advantages n Replace expensive hybrid and mo |
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National Semiconductor |
Wide Bandwidth Dual JFET Input Operational Amplifier n n n n n n n n n n n Internally trimmed offset voltage: Low input bias current: Low input noise voltage: Low input noise current: Wide gain bandwidth: High slew rate: Low supply current: High input impedance: Low total harmonic distortion : Low 1/f |
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National Semiconductor |
JFET Input Operational Amplifiers Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offs |
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National Semiconductor |
Wide Bandwidth Quad JFET Input Operational Amplifiers n n n n n n n n Internally trimmed offset voltage: 5 mV max Low input bias current: 50 pA Low input noise current: Wide gain bandwidth: 4 MHz High slew rate: 13 V/µs Low supply current: 7.2 mA High input impedance: 1012Ω Low total harmonic distortion |
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National Semiconductor |
Monolithic Sample-and-Hold Circuits n Operates from ±5V to ±18V supplies n Less than 10 µs acquisition time n TTL, PMOS, CMOS compatible logic input n 0.5 mV typical hold step at Ch = 0.01 µF n Low input offset n 0.002% gain accuracy n Low output noise in hold mode n Input characterist |
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National Semiconductor |
Wide Bandwidth Quad JFET Input Operational Amplifiers n n n n n n n n Internally trimmed offset voltage: 5 mV max Low input bias current: 50 pA Low input noise current: Wide gain bandwidth: 4 MHz High slew rate: 13 V/µs Low supply current: 7.2 mA High input impedance: 1012Ω Low total harmonic distortion |
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National Semiconductor |
Monolithic Sample-and-Hold Circuits n Operates from ±5V to ±18V supplies n Less than 10 µs acquisition time n TTL, PMOS, CMOS compatible logic input n 0.5 mV typical hold step at Ch = 0.01 µF n Low input offset n 0.002% gain accuracy n Low output noise in hold mode n Input characterist |
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National Semiconductor |
quad JFET analog switch • Constant ON resistance for signals ±10V and 100 kHz < • tOFF tON. break before make action • Open switch isolation at 1.0 MHz • < 1.0 nA leakage in OFF state -50 dB • TTL. DTL. RTL direct drive compatibility • Single disable pin turns all sWitc |
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National Semiconductor |
Voltage Comparators Y Eliminates input current errors Y Interchangeable with LM111 Y No need for input current buffering Schematic Diagram Note Do Not Ground Strobe Pin or Balance Strobe Pin See Note 7 Connection Diagram Metal Can Package TL H 5703 – 2 |
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National Semiconductor |
JFET Input Operational Amplifiers Advantages n Replace expensive hybrid and module FET op amps n Rugged JFETs allow blow-out free handling compared with MOSFET input devices n Excellent for low noise applications using either high or low source impedance — very low 1/f corner n Offs |
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