| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
National Semiconductor |
Dual Low Voltage Differential Signaling Driver n n n n n Ultra low power dissipation Operates above 155.5 Mbps Standard TIA/EIA-644 8 Lead SOIC Package saves space Low Differential Output Swing typical 340 mV Connection Diagram DS100013-1 Order Number DS90C401M See NS Package Number M08A Func |
|
|
|
|
National Semiconductor |
2X2 800 Mbps LVDS Crosspoint Switch n Low jitter 800 Mbps fully differential data path n 75 ps (typ) of pk-pk jitter with PRBS = 223−1 data pattern at 800 Mbps n Single +3.3 V Supply n Less than 330 mW (typ) total power dissipation n Non-blocking ’’Switch Architecture’’ n Balanced outp |
|
|
|
|
National Semiconductor |
LVDS Transmitter 24-Bit Color Flat Panel Display Link n n n n n n n n n Up to 140 Megabyte/sec Bandwidth Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI Low power CMOS design Power down mode PLL requires no external components Low profile 56-lead TSSOP package Rising edge da |
|
|
|
|
National Semiconductor |
LVDS 24-Bit Color Flat Panel Display Link n n n n n n n n n n n n n 20 to 65 MHz shift clk support Up to 227 Mbytes/s bandwidth Cable size is reduced to save cost 290 mV swing LVDS devices for low EMI Low power CMOS design ( < 550 mW typ) Power-down mode saves power ( < 0.25 mW) PLL requires |
|
|
|
|
National Semiconductor |
LVDS Quad CMOS Differential Line Driver n n n n n n n n > 155.5 Mbps (77.7 MHz) switching rates High impedance LVDS outputs with power-off ± 350 mV differential signaling Ultra low power dissipation 400 ps maximum differential skew (5V, 25˚C) 3.5 ns maximum propagation delay Industrial op |
|
|
|
|
National Semiconductor |
LVDS 18-Bit Color Flat Panel Display Link |
|
|
|
|
National Semiconductor |
LVDS 24-Bit Color Flat Panel Display (FPD) Link 65 MHz |
|
|
|
|
National Semiconductor |
+3.3V Programmable LVDS Transmitter n 20 to 65 MHz shift clock support n Rejects > ± 3ns Jitter from VGA chip with less than 225ps output Jitter @65MHz (TJCC) n Best –in –Class Set & Hold Times on TxINPUTs n Tx power consumption < 130 mW (typ) @65MHz Grayscale n > 50% Less Power Dissipat |
|
|
|
|
National Semiconductor |
LVDS Single High Speed Differential Driver n n n n n n n n n n n n n > 600 Mbps (300 MHz) switching rates 0.3 ns typical differential skew 0.7 ns maximum differential skew 1.5 ns maximum propagation delay 3.3V power supply design ± 355 mV differential signaling Low power dissipation (23 mW @ |
|
|
|
|
National Semiconductor |
16-40 MHz 10 Bit Bus LVDS Serializer/Deserializer n n n n n n n n n n Guaranteed transition every data transfer cycle Single differential pair eliminates multi-channel skew Flow-through pinout for easy PCB layout 400 Mbps serial Bus LVDS bandwidth (at 40 MHz clock) 10-bit parallel interface for 1 by |
|
|
|
|
National Semiconductor |
LVDS Transmitter 24-Bit Color Flat Panel Display Link n n n n n n n n n Up to 140 Megabyte/sec Bandwidth Narrow bus reduces cable size and cost 290 mV swing LVDS devices for low EMI Low power CMOS design Power-down mode PLL requires no external components Low profile 56-lead TSSOP package Falling edge d |
|
|
|
|
National Semiconductor |
+3.3V Rising Edge Data Strobe LVDS n 20 to 75 MHz shift clock support n 50% duty cycle on receiver output clock n Best –in –Class Set & Hold Times on TxINPUTs and RxOUTPUTs n Low power consumption n Tx + Rx Power-down mode < 400µW (max) n ± 1V common mode range (around +1.2V) n Narrow b |
|
|
|
|
National Semiconductor |
28-Bit Channel Link n n n n n n n n n n n n n 20 to 85 MHZ shift clock support 50% duty cycle on receiver output clock Best –in –Class Set & Hold Times on TxINPUTs Low power consumption ± 1V common mode range (around +1.2V) Narrow bus reduces cable size and cost Up to 2.3 |
|
|
|
|
National Semiconductor |
28-Bit Channel Link |
|
|
|
|
National Semiconductor |
5-35MHz DC-Balanced 24-Bit LVDS Serializer and Deserializer pre-emphasis to boost signals over longer distances using lossy cables. Internal DC balanced encoding/decoding is used to support AC-Coupled interconnects. n User selectable clock edge for parallel data on both Transmitter and Receiver n Internal DC |
|
|
|
|
National Semiconductor |
+3.3V Programmable LVDS Transmitter n 20 to 85 MHz shift clock support n Best –in –Class Set & Hold Times on TxINPUTs n Tx power consumption < 130 mW (typ) @85MHz Grayscale n Tx Power-down mode < 200µW (max) n Supports VGA, SVGA, XGA and Single/Dual Pixel SXGA. n Narrow bus reduces cable |
|
|
|
|
National Semiconductor |
28-Bit Channel Link Added new pages to the original 1 page. modified RCOH and RCOL min limits. (TxINPUT) TSSOP ) / 0.8mm (FBGA) DS90CR288A 345mV (typ) 2.38Gbit/s 1.2V ( 56 Order Number DS90CR287MTD or DS90CR287SLC 3.3V Rising Edge Data Strobe LVDS 28-Bit Ch |
|
|
|
|
National Semiconductor |
LVDS 18-Bit Color Flat Panel Display Link |
|
|
|
|
National Semiconductor |
3V LVDS Quad CMOS Differential Line Receiver n n n n n n n n n n n n n n > 400 Mbps (200 MHz) switching rates Flow-through pinout simplifies PCB layout 150 ps channel-to-channel skew (typical) 100 ps differential skew (typical) 2.7 ns maximum propagation delay 3.3V power supply design High imp |
|
|
|
|
National Semiconductor |
4 Channel Bus LVDS Transceiver a flow through pin out which allows easy PCB routing for short stubs between its pins and the connector. The driver translates 3V LVTTL levels (single-ended) to differential Bus LVDS (BLVDS) output levels. This allows for high speed operation while c |
|