| No. | Partie # | Fabricant | Description | Fiche Technique |
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National Semiconductor |
DUAL 1-OF-4 DECODER Y Y Y Y Multifunction capability Mutually exclusive outputs Demultiplexing capability Active low enable for each decoder Connection Diagram Dual-In-Line Package Logic Symbol TL F 10209 – 2 TL F 10209 – 1 VCC e Pin 16 GND e Pin 8 DataShee Orde |
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National Semiconductor |
Retriggerable One Shot Y Y Y Y Y Y Y Y High speed operation input repetition rate l 10 MHz Flexibility of operation optional retriggering lock-out capability Output pulse width range 50 ns to % Leading or trailing edge triggering Complementary outputs inputs Input clampi |
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National Semiconductor |
Quad 2-Line to 1-Line Data Selectors / Multiplexers Y Y Pin-for-pin with popular DM54157 74157 Buffered inputs and outputs Expand any data input point Multiplex dual-data buses Generate four functions of two variables (one variable is common) Source programmable counters Alternate Military Aerospace |
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National Semiconductor |
Dual Retriggerable Resettable Monostable Multivibrator Y Y Y Y Y Y Y Y Retriggerable 0% to 100% duty cycle DC level triggering insensitive to transition times Leading or trailing-edge triggering Complementary outputs with active pull-ups Pulse width compensation for DVCC and DTA 50 ns to % output pulse |
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National Semiconductor |
5-Bit Comparator Distributors for availability and specifications Supply Voltage Input Voltage Operating Free Air Temperature Range Military Commercial Storage Temperature Range 7V 5 5V b 55 C to a 125 C 0 C to a 70 C b 65 C to a 150 C Note The ‘‘Absolute Maximum Ra |
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National Semiconductor |
7-Segment Decoder/Driver/Latch means that data can be routed directly from high speed counters and frequency dividers into the display without slowing down the system clock or providing intermediate data storage The latch decoder combination is a simple system which drives LED dis |
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National Semiconductor |
Dual 8-Bit Shift Register 1) additional gating is provided at the input to both shift registers so that the input is easily multiplexed between two sources 2) the clock of each register may be provided separately or together 3) both the true and complementary outputs are prov |
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