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Nanya Techology |
(NT5DSxxMxBx) 256Mb DDR SDRAM CAS Latency and Frequency CAS Latency 3 2.5 Maximum Operating Frequency (MHz) DDR400B (-5T) 200 166 • • • • • • • • • • • • • • Double data rate architecture: two data transfers per clock cycle • Bidirectional data strobe (DQS) is transmitted and r |
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Nanya |
Commercial and Industrial DDR3 4Gb SDRAM Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes Power |
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Nanya Technology |
(NT5DSxxMxAx) 128Mb DDR333/300 SDRAM CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR333 DDR300 (-6) (-66) 2 133 133 2.5 166 150 * Values are nominal (exact tCK should be used). CAS Latency • Double data rate architecture: two data transfers per clock cycle • Bidirectio |
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Nanya Techology |
256Mb SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 (5T) (6K/6KL) 133 166 166 200 - • • • • • • • • • • • • • • • DDR 256M bit, die C, based on 110nm design rules • Double data rate architecture: two data t |
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Nanya |
1Gb DDR2 SDRAM (1) posted CAS with additive latency, (2) write latency = read latency -1, (3) normal and weak strength data-output driver, (4) variable data-output impedance adjustment and (5) an ODT (On-Die Termination) function. All of the control and address i |
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Nanya |
2Gb DDR3 SDRAM B-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
4Gb DDR3 SDRAM B-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
Commercial and Industrial DDR3 4Gb SDRAM Basis DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes Power |
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Nanya |
2Gb DDR3 SDRAM D-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
Industrial and Automotive DDR3(L) 2Gb SDRAM JEDEC DDR3 Compliant - 8n Prefetch Architecture - Differential Clock(CK/) and Data Strobe(DQS/) - Double-data rate on DQs, DQS and DM Data Integrity - Auto Self Refresh (ASR) by DRAM built-in TS - Auto Refresh and Self Refresh Modes Power |
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Nanya Technology |
Fast Page Mode DRAM ....................................................................................................................................................................................................03 Product Family .................................... |
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Nanya Technology |
CMOS with Rxtended Data Out .......................................................................................................................................................................03 Product Family ................................................................. |
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Nanya Technology |
Fast Page Mode with EDO DRAM ................................................................................................3 3. Product Family........................................................................................3 4. Pin Configuration......................... |
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Nanya |
2Gb DDR3 SDRAM G-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya Techology |
(NT5DSxxMxBx) 512Mb DDR SDRAM CAS Latency and Frequency CAS Latency 2 2.5 3 Maximum Operating Frequency (MHz) DDR400 DDR333 DDR266B (5T) (6K) (75B) 133 100 166 166 133 200 - • • • • • • • • • • • • • • DDR 512M bit, die B, based on 110nm design rules • Double data rate architec |
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Nanya Techology |
(NT5DS16M8AT / NT5DS32M4AT) 128Mb DDR SDRAM CAS Latency and Frequency Maximum Operating Frequency (MHz)* DDR266A DDR266B DDR200 (-7K) (-75B) (-8B) 2 133 100 100 2.5 143 133 125 * Values are nominal (exact tCK should be used). CAS Latency • Double data rate architecture: two data transfers per |
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Nanya |
4Gb DDR3 SDRAM B-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
2Gb DDR3 SDRAM H-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
1Gb DDR3 SDRAM A-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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Nanya |
2Gb DDR3 SDRAM D-Die and all of the control and address inputs are synchronized with a pair of externally supplied differential clocks. Inputs are latched at the cross point of differential clocks (CK rising and falling). All I/Os are synchronized with a single ended |
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