No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
|
|
NXP |
FIELD PROGRAMMABLE LOGIC SEQUENCER |
|
|
|
NXP |
Programmable logic array 22 x 42 x 10 • I/O propagation delay: 30ns (max.) • 12 inputs • 42 AND gates • 10 OR gates • 10 bidirectional I/O lines • Active-High or -Low outputs • 42 product terms: – 32 logic terms – 10 control terms PIN CONFIGURATIONS N Package I0 1 I1 2 I2 3 I3 4 I4 5 I |
|
|
|
NXP |
FIELD PROGRAMMABLE LOGIC SEQUENCER |
|
|
|
NXP |
Programmable logic sequencer 16 x 45 x 12 8 registered I/O outputs (F) in conjunction with 4 bidirectional I/O lines (B). These yield variable I/O gate and register configurations via control gates (D, L) ranging from 16 inputs to 12 outputs. The AND/OR arrays consist of 32 logic AND gates, |
|
|
|
NXP |
Programmable Logic Sequencer |
|
|
|
NXP |
(PLS100 / PLS101) Programmable logic arrays • Field-programmable (Ni-Cr link) • Input variables: 16 • Output functions: 8 • Product terms: 48 • I/O propagation delay: 50ns (max.) • Power dissipation: 600mW (typ.) • Input loading: –100µA (max.) • Chip Enable input • Output option: – PLS100: 3- |
|
|
|
NXP |
(PLS100 / PLS101) Programmable logic arrays • Field-programmable (Ni-Cr link) • Input variables: 16 • Output functions: 8 • Product terms: 48 • I/O propagation delay: 50ns (max.) • Power dissipation: 600mW (typ.) • Input loading: –100µA (max.) • Chip Enable input • Output option: – PLS100: 3- |
|
|
|
NXP |
Field-Programmable Logic Sequencer |
|
|
|
NXP |
FIELD PROGRAMMABLE LOGIC SEQUENCER |
|