NXP MIM fiche technique

No.	Partie #	Fabricant	Description
1	MIMXRT1171CVM8A	NXP	Crossover Processors NXP’s advanced 2. implementation of a high performance Arm 3. Cortex®-M7 core operating at speeds up to 800 MHz and a power efficient Cortex®-M4 core up to 400 MHz. The i.MX RT1170 processor has 2 MB on-chip RAM in 4. total, including a 768 KB
2	MIMXRT1052DVL6B	NXP	i.MX RT1050 Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 5 2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1. Block diagram . . . . .
3	MIMX8MM6DVTLZAA	NXP	8M Mini Applications Processor with 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . 6 2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connec
4	MIMXRT1173CVM8A	NXP	Crossover Processors NXP’s advanced 2. implementation of a high performance Arm 3. Cortex®-M7 core operating at speeds up to 800 MHz and a power efficient Cortex®-M4 core up to 400 MHz. The i.MX RT1170 processor has 2 MB on-chip RAM in 4. total, including a 768 KB
5	MIMX8MD6CVAHZAB	NXP	Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit
6	MIMX8MM5CVTKZAA	NXP	i.MX 8M Mini Applications Processor with 2. 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connect
7	MIMXRT1175AVM8A	NXP	Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The i.MX RT1170 is a new high-end processor of the 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 1.3. Package marking information . . . . . . . . . . . .
8	MIMXRT1171AVM8A	NXP	Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The i.MX RT1170 is a new high-end processor of the 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 1.3. Package marking information . . . . . . . . . . . .
9	MIMX8ML3DVNLZAB	NXP	Applications Processor (Sheet 1 of 4) Subsystem Cortex®-A53 MPCore platform Cortex®-M7 core platform Image Sensor Processor (ISP) External memory interface On-chip memory Features Quad Cortex®-A53 processors operation up to 1.8 GHz • 32 KB L1 Instruction Cache • 32 KB L1
10	MIMX8MQ6DVAJZAA	NXP	i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit
11	MIMX8MD7DVAJZAA	NXP	i.MX 8M Dual / 8M QuadLite / 8M Quad Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit
12	MIMXRT1051DVL6B	NXP	i.MX RT1050 Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 5 2. Architectural overview . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 2.1. Block diagram . . . . .
13	MIMX8MD6CVAHZAA	NXP	Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit
14	MIMX8MD7CVAHZAA	NXP	Applications Processors Feature Quad symmetric Cortex-A53 processors: • 32 KB L1 Instruction Cache • 32 KB L1 Data Cache • Support L1 cache RAMs protection with parity/ECC Support of 64-bit Armv8-A architecture: • 1 MB unified L2 cache • Support L2 cache RAMs protection wit
15	MIMX8MM2DVTLZAA	NXP	8M Mini Applications Processor with 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . 6 2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connec
16	MIMX8MM4DVTLZAA	NXP	8M Mini Applications Processor with 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . . 6 2. Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connec
17	MIMXRT1172DVMAA	NXP	i.MX RT1170 Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The i.MX RT1170 is a new high-end processor of the 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 1.3. Package marking information . . . . . . . . . . . .
18	MIMXRT1175DVMAA	NXP	i.MX RT1170 Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 The i.MX RT1170 is a new high-end processor of the 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 1.3. Package marking information . . . . . . . . . . . .
19	MIMX8MM4CVTKZAA	NXP	i.MX 8M Mini Applications Processor with 2. 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 Modules list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 high-performance processing while optimized for lowest 2.1. Recommended connect
20	MIMXRT1061DVL6A	NXP	i.MX RT1060 Crossover Processors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 1.2. Ordering information . . . . . . . . . . . . . . . . . . . . . . . 6 2. Architectural Overview . . . . . . . . . . . . . . . . . . . . . . . . . 12 MHz to provide high CPU perfor