| No. | Partie # | Fabricant | Description | Fiche Technique |
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NXP |
PNP power transistor • High current (max. 1.5 A) • Low voltage (max. 80 V). APPLICATIONS • Driver stages in television circuits. DESCRIPTION PNP power transistor in a TO-126; SOT32 plastic package. NPN complement: BD230. handbook, halfpage BD231 PINNING PIN 1 2 3 emitte |
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NXP |
32-bit ARM Cortex-M4/M0 MCU and a high level of support block integration. The ARM Cortex-M4 CPU incorporates a 3-stage pipeline, uses a Harva |
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NXP |
32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as |
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NXP |
32-bit ARM Cortex-M4/M0 MCU with AES engine, a quad SPI Flash Interface (SPIFI), advanced configurable peripherals such as the State Configurable Timer (SCT) and the Serial General Purpose I/O (SGPIO) interface, two High-speed USB controllers, Ethernet, LCD, an external memory |
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NXP |
NPN power transistor • High current (max. 1.5 A) • Low voltage (max. 80 V). APPLICATIONS • Driver stages in television circuits. DESCRIPTION handbook, halfpage BD230 PINNING PIN 1 2 3 emitter collector, connected to metal part of mounting surface base DESCRIPTION NPN p |
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NXP |
32-bit ARM Cortex-M3 MCU and a high level of support block integration. The LPC185x/3x/2x/1x operate at CPU frequencies of up to 180 MHz. The ARM Cortex-M3 CPU incorporates a 3-stage pipeline and uses a Harvard architecture with separate local instruction and data buses as |
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