| No. | Partie # | Fabricant | Description | Fiche Technique |
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NXP |
Octal bus transceiver/register |
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NXP |
Quad buffer four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling one of the 3-state outputs. 2. Features and benefits Quad bus interface 3-state buffers Live insertion and extraction permitted Output capability: HIGH 32 mA; LOW +64 mA Pow |
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NXP |
Octal buffer/line driver • Octal bus interface • 3-State buffers • Live insertion/extraction permitted • Outputs include series resistance of 30Ω, making external termination resistors unnecessary DESCRIPTION The 74ABT2244 high-performance BiCMOS device combines low static |
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NXP |
Quad 2-input AND gate and benefits Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C 3. Ordering information |
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NXP |
16-bit buffer/line driver four output enable inputs (1OE, 2OE, 3OE, 4OE), each controlling four of the 3-state outputs. The 74ABT162244 is designed with 30 series resistance in both the upper and lower output structures. This design reduces line noise in applications such a |
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NXP |
16-bit bus transceiver two output enable (1OE, 2OE) inputs for easy cascading and two direction (1DIR, 2DIR) inputs for direction control. 2. Features and benefits 16-bit bidirectional bus interface Multiple VCC and GND pins minimize switching noise Power-up 3-state |
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NXP |
Octal D-type flip-flop • Eight edge-triggered D-type flip-flops • Buffered common clock • Buffered asynchronous Master Reset • Power-up reset • See 74ABT377 for clock enable version • See 74ABT373 for transparent latch version • See 74ABT374 for 3-State version • ESD prot |
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NXP |
Octal transceiver • Combines 74ABT245 and 74ABT374 type functions in one device • Independent registers for A and B buses • Multiplexed real-time and stored data • Output capability: +64mA/ –32mA • Power-up 3-state • Power-up reset • Live insertion/extraction permitted |
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NXP |
3.3V ABT 16-bit bus transceiver • 16-bit universal bus interface • 3-State buffers • Output capability: +64mA/-32mA • TTL input and output switching levels • Input and output interface capability to systems at 5V supply • Bus-hold data inputs eliminate the need for external pull-u |
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NXP |
Quad 2-input NAND gate and benefits Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C 3. Ordering information |
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NXP |
Quad 2-input NOR gate A1 A2 B1 B2 A3 B3 11 13 12 Y0 Y1 Y2 Y3 SF00010 VCC = Pin 14 GND = Pin 7 1 4 10 13 FUNCTION TABLE INPUTS SA00362 OUTPUT Bn L H L H Yn H L L L An L L H H NOTES: H = High voltage level L = Low voltage level ORDERING INFORMATION PACKAGES 14-P |
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NXP |
Hex inverter and benefits Latch-up protection exceeds 500 mA per JESD78B class II level A ESD protection: HBM JESD22-A114F exceeds 2000 V MM JESD22-A115-A exceeds 200 V Multiple package options Specified from 40 C to +85 C 3. Ordering information |
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NXP |
Triple 3-input NAND gate 2 B0 13 C0 A1 B1 C1 A2 B2 VCC = Pin 14 GND = Pin 7 C2 3 4 5 9 10 11 8 Y2 6 Y1 12 Y0 SV00059 FUNCTION TABLE INPUTS Bn L L H H L L H H Cn L H L H L H L H OUTPUTS Yn H H H H H H H L LOGIC DIAGRAM L H H H H NOTES: H = High voltage level L = Low volt |
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NXP |
16-Bit bus transceiver • 16-bit bidirectional bus interface • Power-up 3-State • Multiple VCC and GND pins minimize switching noise • 3-State buffers • Output capability: +12mA/ –32mA • Latch-up protection exceeds 500mA per JEDEC Std 17 • ESD protection exceeds 2000 V per |
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NXP |
18-bit universal bus transceiver • 18-bit bidirectional bus interface • 3-State buffers • 74ABTH16500C incorporates bus-hold data inputs which • Output capability: +64mA/-32mA • TTL input and output switching levels • Live insertion/extraction permitted • Power-up reset • Power-up |
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NXP |
16-bit buffer/line driver • Power-up 3-State • Multiple VCC and GND pins minimize switching noise • Provides ideal interface and increases fan-out of MOS • • 74ABTH16541 incorporates bus-hold data inputs which eliminate • Latch-up protection exceeds 500mA per Jedec Std 17 • |
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NXP |
Octal D-type flip-flop • Ideal for addressable register applications • 8-bit positive edge-triggered register • Enable for address and data synchronization applications • Output capability: +64mA/-32mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD prot |
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NXP |
Synchronizing dual D-type flip-flop • Metastable immune characteristics • Pin compatible with 74F74 and 74F5074 • Typical fMAX = 200MHz • Output skew guaranteed less than 2.0ns • High source current (IOH = 15mA) ideal for clock driver applications PIN CONFIGURATION RD0 D0 CP0 SD0 Q0 |
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NXP |
Octal buffer • Octal bus interface • 3-State buffers • Live insertion/extraction permitted • Efficient pinout to facilitate PC board layout • Output capability: +64mA/ –32mA • Latch-up protection exceeds 500mA per Jedec JC40.2 Std 17 • ESD protection exceeds 2000 |
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NXP |
Octal D-type flip-flop |
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