| No. | Partie # | Fabricant | Description | Fiche Technique |
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Motorola |
QUAD 2-INPUT AND GATE |
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Motorola |
8-BIT SHIFT REGISTERS D D1 20 19 18 17 B/QB D/QD F/QF H/QH 16 15 14 13 Q/H CLOCK 12 11 DS SE D1 B/QB D/QD F/QF H/GH Q/H G CK S/P D0 A/QA C/QC E/QE G/QG OE CLR 12 REGISTER S/P ENABLE 3 4 5 6 7 8 9 10 D0 A/QA C/QC E/QE G/QG OUTPUT CLEAR GND ENABLE GUARANTEED OPERAT |
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Motorola |
4-BIT ARITHMETIC LOGIC Comparator Output Carry Generator (Active LOW) Output Carry Propagate (Active LOW) Output Carry Output 1.5 U.L. 2.0 U.L. 0.5 U.L. 2.5 U.L. 10 U.L. Open Collector 10 U.L. 10 U.L. 10 U.L. 0.75 U.L. 1.0 U.L. 0.25 U.L. 1.25 U.L. 5 (2.5) U.L. 5 (2.5) U. |
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Motorola Semiconductor |
(SN75451 - SN75454) Dual Peripheral Drivers |
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Motorola |
8-BIT SHIFT/STORAGE REGISTER are described below: 1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control (S0, S1) and data inputs (DS0, DS7, I/O0 –I/O7) |
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Motorola |
QUAD 2-INPUT NAND GATE ode Voltage 54 VOH Output HIGH Voltage 74 – 0.65 – 1.5 2.5 3.5 2.7 3.5 V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 74 0.25 0.4 0.35 0.5 V IOL = 4.0 mA VC |
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Motorola |
HEX INVERTER 6.6 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VC |
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Motorola |
QUAD 2-INPUT OR GATE |
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Motorola |
DUAL 4-INPUT NAND GATE put HIGH Voltage – 0.65 – 1.5 V VCC = MIN, IIN = – 18 mA 54 2.5 3.5 74 2.7 3.5 V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 74 0.25 0.4 0.35 0.5 V IOL = 4.0 mA V IOL = 8.0 mA VCC = VCC M |
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Motorola |
BCD TO 7-SEGMENT DECODER |
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Motorola |
SYNCHRONOUS 4-BIT UP/DOWN COUNTER an internal carry lookahead for cascading purposes. By clocking all flip-flops simultaneously so the outputs change coincident with each other (when instructed to do so by the count enable inputs and internal gating) synchronous operation is provided |
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Motorola |
QUAD EIA-485 LINE RECEIVER high input impedance, input hysteresis for increased noise immunity, and input sensitivity of ± 200 mV over a common mode input voltage range of –12 V to 12 V. The SN75175 is designed for optimum performance when used with the SN75172 or SN75174 quad |
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Motorola |
Triple 3 Input AND Gate 0.35 0.5 20 IIH IIL ICC V µA mA mA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VCC = MIN, I |
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Motorola Semiconductor |
(SN74LS783 / SN74LS785) Synchronous Address Multiplexer |
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Motorola |
BCD TO 7-SEGMENT DECODER/DRIVER hstand 15 V with a maximum reverse current of 250 µA. Indicator segments requiring up to 24 mA of current may be driven directly from the SN74LS47 high performance output transistors. Display patterns for BCD input counts above nine are unique symbol |
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Motorola |
10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS |
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Motorola |
DUAL 1-OF-4 DECODER/ DEMULTIPLEXER |
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Motorola |
8-BIT MAGNITUDE COMPARATORS |
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Motorola |
QUAD 3-STATE BUFFERS |
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Motorola |
4-BIT BINARY FULL ADDER standard corner power pins. CONNECTION DIAGRAM DIP (TOP VIEW) B4 Σ4 C4 C0 GND B1 A1 Σ1 16 15 14 13 12 11 10 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 12 A4 Σ3 3 4 56 A3 B3 VCC Σ2 78 B2 A2 |
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