No. | Partie # | Fabricant | Description | Fiche Technique |
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Motorola |
3.3V/2.5V LVCMOS 1:12 Clock Fanout Buffer n and computing applications • Pin and function compatible to MPC948 FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A Functional Description The MPC9448 is specifically designed to distribute LVCMOS compatible clock signals up to a frequency of 350 MHz. E |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER to aid in system debug and test. The PECL reference input pins can be interfaced to a test signal and the PLL can be bypassed to allow the designer to drive the MPC992 outputs directly. This allows for single stepping in a system functional debug mod |
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Motorola |
(MPC562 / MPC563 / MPC564) RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family. As shown in the block diagram, they are composed of: • High performance CPU system — High performance core • Single issue integer core • Compatible with |
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Motorola |
800 MHz Low Voltage PECL Clock Synthesizer • • • • • • • • • • • • • • • 50 MHz to 800 MHz1 synthesized clock output signal Differential PECL output LVCMOS compatible control inputs On-chip crystal oscillator for reference frequency generation Alternative LVCMOS compatible reference clock inp |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER • 9 outputs LVCMOS PLL clock generator MPC9350 LOW VOLTAGE 3.3V AND 2.5V PLL CLOCK GENERATOR Freescale Semiconductor, Inc... Temperature range –40°C to +85°C Functional Description The MPC9350 generates high frequency clock signals and provides n |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER a fully integrated PLL with no external components required. With output frequencies of up to 180MHz and eleven low skew outputs the MPC952 is well suited for high performance designs. The device employs a fully differential PLL design to optimize ji |
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Motorola |
PowerPC 604e-TM RISC Microprocessor Technical Summary including a block diagram showing the major functional components. It provides information about how the 604e implementation complies with the PowerPC™ architecture definition. This document is divided into two parts: • Part 1,“PowerPC 604e Microproc |
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Motorola |
LOW VOLTAGE 1:12 CLOCK DISTRIBUTION CHIP the capability to select either a differential LVPECL or a LVTTL compatible input. The 12 outputs are LVCMOS or LVTTL compatible and feature the drive strength to drive 50Ω series terminated transmission lines. With output –to –output skews of 350ps, t |
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Motorola |
MPC8272 PowerQUICC II Family Hardware Specifications Dual-issue integer (G2_LE) core — A core version of the MPC603e microprocessor — System core microprocessor supporting frequencies of 266-400 MHz — Separate 16-Kbyte data and instruction caches: – Four-way set associative – Physically addressed – LRU |
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Motorola |
(MPC562 / MPC563 / MPC564) RISC MCU Including Peripheral Pin Multiplexing with Flash and Code Compression Options The MPC561/MPC562 / MPC563/MPC564 are members of the Motorola MPC500 RISC Microcontroller family. As shown in the block diagram, they are composed of: • High performance CPU system — High performance core • Single issue integer core • Compatible with |
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Motorola |
2.5V and 3.3V LVCMOS Clock Fanout Buffer • Configurable 10 outputs LVCMOS clock distribution buffer MPC9446 LOW VOLTAGE SINGLE OR DUAL SUPPLY 2.5V AND 3.3V LVCMOS CLOCK DISTRIBUTION BUFFER Freescale Semiconductor, Inc... • Compatible to single, dual and mixed 3.3V/2.5V voltage supply • |
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Motorola Semiconductor |
RISC Microprocessor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .3 3. Comparison with the MPC7447A, MPC7447, MPC7445, and MPC7441 . . . . . . . . . . . . . . . . . . . . . . .7 4. General Parameters . . . . . . . . . . . . . . . . . . . . . . |
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Motorola Semiconductor |
PowerQUICC II Pro Integrated Host Processor Hardware Specifications Figure 1 shows the major functional units within the MPC8347EA. Security DUART Dual I2C Timers GPIO e300 Core Interrupt Controller 32KB D-Cache 32KB I-Cache DDR SDRAM Controller Local Bus High-Speed USB 2.0 Dual Role Host 10/100/1000 Ethernet |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER an extensive level of frequency programmability between the 12 outputs as well as the input vs output relationships. Using the select lines output frequency ratios of 1:1, 2:1, 3:1, 3:2, 4:1, 4:3, 5:1, 5:2, 5:3, 6:1 and 6:5 between outputs |
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Motorola Inc |
LOW VOLTAGE PLL CLOCK DRIVER make the MPC958 ideal for use as a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance. The MR/OE input pin will tristate the output buffers when driven “high”. The MPC958 is fully 3.3V c |
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Motorola |
MPC5200 Hardware Specifications .......................................1 Electrical and Thermal Characteristics..............................5 Package Description ..................60 System Design Information ........69 Ordering Information ..................74 Document Revision H |
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Motorola |
Intelligent Dynamic Clock Switch (IDCS) PLL Clock Driver • Fully Integrated PLL MPC99J93 Freescale Semiconductor, Inc... FA SUFFIX 32--LEAD LQFP PACKAGE CASE 873A • • • • • Intelligent Dynamic Clock Switch LVPECL Clock Outputs LVCMOS Control I/O 3.3V Operation 32--Lead LQFP Packaging Functional Desc |
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Motorola |
Hardware Specifications Section 3, “Maximum Tolerated Ratings” Section 4, “Thermal Characteristics” Section 5, “Power Dissipation” Section 6, “DC Characteristics” Section 7, “Thermal Calculation and Measurement” Section 8, “Layout Practices” Section 9, “Bus Signal Timing” |
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Motorola |
LOW VOLTAGE PLL CLOCK DRIVER of the oscilliscope to remove the jitter component. APPLICATIONS INFORMATION MPC932 ‘0’ ‘0’ FBSEL0 FBSEL1 Qn 6 66MHz ‘1’ ‘0’ FBSEL0 FBSEL1 MPC932 Qn 6 83MHz QFB 66MHz Input Ref FB_In 1 66MHz 66MHz Input Ref FB_In QFB 1 66MHz MPC932 ‘1’ ‘0’ |
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