| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Motorola |
4-BIT PARALLEL / SERIAL CONVERTER |
|
|
|
|
Motorola |
TRANSISTOR |
|
|
|
|
Motorola |
Dual 3-Input/3-Output NOR Gate ee the Pin Conversion Tables on page 6 –11 of the Motorola MECL Data Book (DL122/D). 9/96 © Motorola, Inc. 1996 3 –44 REV 6 MC10111 ELECTRICAL CHARACTERISTICS Test Limits Pin Pi Under Test 8 5, 6, 7 5, 6, 7 2 3 4 2 3 4 2 3 4 2 3 4 0.5 –1.060 –1.06 |
|
|
|
|
Motorola |
TRANSISTOR |
|
|
|
|
Motorola Inc |
Silicon Controlled Rectifier n-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to +110°C) Circuit Fusing (t = 8.3 ms) Peak Gate Power Average Gate Power Peak Forward Gate Current Symbol VDRM or VRRM Value 50 100 200 400 600 4 2.55 20 1.65 0.5 0.1 0.2 Amps Amps Amps A2s Watt |
|
|
|
|
Motorola |
1:4 Clock Distribution Chip a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pulldown resistor) the SEL pin will select the differential clock i |
|
|
|
|
Motorola |
Quad Latch |
|
|
|
|
Motorola |
6-BIT UNIVERSAL UP/DOWN COUNTER allow for the cacading of multiple E136’s for wider bit width counters that operate at very nearly the same frequency as the stand alone counter. • 550 MHz Count Frequency • Fully Synchronous Up and Down Counting • Internal 75 kΩ Input Pulldown Resis |
|
|
|
|
Motorola |
1:5 Clock Distribution Chip a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or le |
|
|
|
|
Motorola |
QUINT DIFFERENTIAL LINE RECEIVER |
|
|
|
|
Motorola |
Registered Hex TTL/PECL Translator differential PECL outputs as well as a choice between either a differential PECL clock input or a TTL clock input. The asynchronous master reset control is a PECL level input. With its differential PECL outputs and TTL inputs the H606 device is ideal |
|
|
|
|
Motorola |
Dual 3-Input/3-Output NOR Gate e the Pin Conversion Tables on page 6 –36 of the Motorola MECL Data Book (DL122/D). 3/93 © Motorola, Inc. 1996 3 –187 REV 5 MC10211 ELECTRICAL CHARACTERISTICS Test Limits Pin Pi Under Test 8 5, 6, 7 5, 6, 7 2 3 4 2 3 4 2 3 4 2 3 4 0.5 –1.060 –1.06 |
|
|
|
|
Motorola |
Dual 3-Input 3-Output NOR Gate |
|
|
|
|
Motorola |
Triple 4-3-3-Input Bus Driver |
|
|
|
|
Motorola |
Quad BUS Driver/Receiver |
|
|
|
|
Motorola |
Silicon Controlled Rectifier (TA = 30°C) Peak Non-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to +110°C) Circuit Fusing (t = 8.3 ms) Peak Gate Power Average Gate Power Peak Forward Gate Current Symbol VDRM or VRRM Value 50 100 200 400 600 4 2.55 20 1.65 0.5 0.1 0.2 Amp |
|
|
|
|
Motorola |
Silicon Controlled Rectifier (TA = 30°C) Peak Non-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to +110°C) Circuit Fusing (t = 8.3 ms) Peak Gate Power Average Gate Power Peak Forward Gate Current Symbol VDRM or VRRM Value 50 100 200 400 600 4 2.55 20 1.65 0.5 0.1 0.2 Amp |
|
|
|
|
Motorola |
SCRs 4 AMPERES RMS 50 thru 600 VOLTS (TA = 30°C) Peak Non-repetitive Surge Current (1/2 Cycle, 60 Hz, TJ = –40 to +110°C) Circuit Fusing (t = 8.3 ms) Peak Gate Power Average Gate Power Peak Forward Gate Current Symbol VDRM or VRRM Value 50 100 200 400 600 4 2.55 20 1.65 0.5 0.1 0.2 Amp |
|
|
|
|
Motorola |
Dual Type D Master-Slave Flip-Flop |
|
|
|
|
Motorola |
QUINT DIFFERENTIAL LINE RECEIVER clamp circuitry to cause a defined state if both the inverting and non-inverting inputs are left open; in this case the Q output goes LOW, while the Q output goes HIGH. This feature makes the device ideal for twisted pair applications. If both in |
|