| No. | Partie # | Fabricant | Description | Fiche Technique |
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Motorola |
QUAD 2-INPUT AND GATE |
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Motorola |
8-BIT SHIFT REGISTERS D D1 20 19 18 17 B/QB D/QD F/QF H/QH 16 15 14 13 Q/H CLOCK 12 11 DS SE D1 B/QB D/QD F/QF H/GH Q/H G CK S/P D0 A/QA C/QC E/QE G/QG OE CLR 12 REGISTER S/P ENABLE 3 4 5 6 7 8 9 10 D0 A/QA C/QC E/QE G/QG OUTPUT CLEAR GND ENABLE GUARANTEED OPERAT |
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Motorola |
HEX INVERTER 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA VCC |
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Motorola |
DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP (Set) Load “0” (Reset) L H L H H SD H L L H H D X X X h l Q H L H H L Q L H H L H OUTPUTS SN54LSXXJ SN74LSXXN SN74LSXXD Ceramic Plastic SOIC LOGIC SYMBOL 4 2 3 D SD Q CP CD Q 1 VCC = PIN 14 GND = PIN 7 6 5 12 11 10 D SD Q CP CD Q 13 8 9 * Both out |
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Motorola |
4-BIT ARITHMETIC LOGIC Comparator Output Carry Generator (Active LOW) Output Carry Propagate (Active LOW) Output Carry Output 1.5 U.L. 2.0 U.L. 0.5 U.L. 2.5 U.L. 10 U.L. Open Collector 10 U.L. 10 U.L. 10 U.L. 0.75 U.L. 1.0 U.L. 0.25 U.L. 1.25 U.L. 5 (2.5) U.L. 5 (2.5) U. |
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Motorola |
DUAL 4-INPUT MULTIPLEXER a 7 Za 8 GND 16 1 N SUFFIX PLASTIC CASE 648-08 PIN NAMES S0 E I0, I1 Z Common Select Input Enable (Active LOW) Input Multiplexer Inputs Multiplexer Output (Note b) LOADING (Note a) HIGH 0.5 U.L. 0.5 U.L. 0.5 U.L. 10 U.L. LOW 0.25 U.L. 0.25 U.L. |
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Motorola |
QUAD 2-INPUT NAND GATE |
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Motorola |
PRESETTABLE 4-BIT BINARY UP/DOWN COUNTERS simplifies the design of multi-stage counters, as indicated in Figures a and b. In Figure a, each RC output is used as the clock input for the next higher stage. This configuration is particularly advantageous when the clock source has a limited driv |
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Motorola |
4-STAGE PRESETTABLE RIPPLE COUNTERS makes the circuits usable as programmable counters. The circuits can also be used as 4-bit latches, loading data from the Parallel Data inputs when PL is LOW and storing the data when PL is HIGH. SN54/74LS196 SN54/74LS197 4-STAGE PRESETTABLE RIPPLE |
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Motorola |
BCD TO 7-SEGMENT DECODER quency and duty cycle of the BI input signal or to inhibit the outputs. • Lamp Intensity Modulation Capability (BI/RBO) • Internal Pull-Ups Eliminate Need for External Resistors • Input Clamp Diodes Eliminate High-Speed Termination Effects CONNECTION |
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Motorola |
PRESETTABLE BCD/DECADE UP/DOWN COUNTER peed . . . 40 MHz Typical Count Frequency Synchronous Counting Asynchronous Master Reset and Parallel Load Individual Preset Inputs Cascading Circuitry Internally Provided Input Clamp Diodes Limit High Speed Termination Effects 16 1 N SUFFIX PLASTI |
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Motorola |
4-BIT BINARY FULL ADDER standard corner power pins. CONNECTION DIAGRAM DIP (TOP VIEW) B4 16 Σ4 15 C4 14 C0 13 GND 12 B1 11 A1 10 Σ1 9 NOTE: The Flatpak version has the same pinouts (Connection Diagram) as the Dual In-Line Package. 4-BIT BINARY FULL ADDER WITH FAST CARRY LO |
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Motorola |
8-BIT SHIFT/STORAGE REGISTER are described below: 1. They use eight D-type edge-triggered flip-flops that respond only to the LOW-to-HIGH transition of the Clock (CP). The only timing restriction, therefore, is that the mode control (S0, S1) and data inputs (DS0, DS7, I/O0 –I/O7) |
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Motorola |
4-BIT BINARY COUNTER e. 1 2 3 4 5 6 7 MS NC MS Q2 Q1 NC GND VCC MR MR CP1 CP0 Q0 Q3 14 13 12 11 10 9 8 LS293 SN54/74LS290 SN54/74LS293 DECADE COUNTER; 4-BIT BINARY COUNTER LOW POWER SCHOTTKY 14 1 J SUFFIX CERAMIC CASE 632-08 14 1 14 1 N SUFFIX PLASTIC C |
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Motorola |
QUAD 2-INPUT NAND GATE ode Voltage 54 VOH Output HIGH Voltage 74 – 0.65 – 1.5 2.5 3.5 2.7 3.5 V VCC = MIN, IIN = – 18 mA V VCC = MIN, IOH = MAX, VIN = VIH V or VIL per Truth Table VOL Output LOW Voltage 54, 74 74 0.25 0.4 0.35 0.5 V IOL = 4.0 mA VC |
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Motorola |
DUAL JK NEGATIVE EDGE-TRIGGERED FLIP-FLOP individual J, K, clock, and asynchronous set and clear inputs to each flip-flop. When the clock goes HIGH, the inputs are enabled and data will be accepted. The logic level of the J and K inputs may be allowed to change when the clock pulse is HIGH a |
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Motorola |
DECADE COUNTER a) HIGH CP0 CP1 CP1 MR1, MR2 MS1, MS2 Q0 Q1, Q2, Q3 Clock (Active LOW going edge) Input to ÷2 Section Clock (Active LOW going edge) Input to ÷5 Section (LS90), ÷6 Section (LS92) Clock (Active LOW going edge) Input to ÷8 Section (LS93) Master Reset (C |
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Motorola |
HEX INVERTER 6.6 0.35 0.5 20 IIH IIL IOS ICC V µA mA mA mA 2.7 3.5 0.25 0.4 V V 2.5 – 0.65 3.5 0.8 – 1.5 V V Min 2.0 0.7 V Typ Max U i Unit V T Test C Conditions di i Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input p LOW Voltage g for All Inputs VC |
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Motorola |
LOW-VOLTAGE CMOS O3 10 GND M SUFFIX 20 –LEAD SOIC EIAJ PACKAGE CASE 967 –01 1OE 1 2OE 2 18 19 Figure 1. 20 –Lead Pinout (Top View) 1D0 1O0 2D0 17 3 PIN NAMES 2O0 Pins nOE 1Dn, 2Dn 1On, 2On Function Output Enable Inputs Data Inputs 3 –State Outputs 1D1 4 16 1O1 |
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Motorola |
QUAD 2-INPUT NAND GATE 4.4 0.35 0.5 20 IIH IIL ICC V µA mA mA 54, 74 54, 74 0.25 – 0.65 0.8 – 1.5 100 0.4 V µA V Min 2.0 0.7 V Typ Max Unit V Test Conditions Guaranteed Input HIGH Voltage for All Inputs Guaranteed Input LOW Voltage for All Inputs VCC = MIN, IIN = – 18 mA |
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