| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Lattice Semiconductor |
Zero Delay And Fan-Out Buffer CleanClock™ PLL Ultra Low Period Jitter 2.5ps Ultra Low Phase Jitter 6.5ps Fully Integrated High-Performance PLL • • • • • Programmable lock detect Four output dividers Programmable on-chip loop filter Compatible with Spread Spectrum clocks Int |
|
|
|
|
Lattice Semiconductor |
In-System Programmable Power Supply ■ Monitor and Control Multiple Power Supplies • • • • Simultaneously monitors up to 12 power supplies Sequence controller for power-up conditions Provides eight output control signals Programmable digital and analog circuitry Application Block Diagr |
|
|
|
|
Lattice Semiconductor |
High-Speed Asynchronous E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS ® TECHNOLOGY — 7.5 ns Maximum Propagation Delay — Fmax = 83.3 MHz — 9 ns Maximum from Clock Input to Data Output — TTL Compatible 8 mA Outputs — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR |
|
|
|
|
Lattice Semiconductor |
In-System Programmable High Density PLD Functional Block Diagram OutputDISCALOLNTDIENVUIECDERoutingSPool Output Routing Pool • HIGH-DENSITY PROGRAMMABLE LOGIC — High-Speed Global Interconnect — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — Wide Input Gating for Fa |
|
|
|
|
Lattice Semiconductor |
In-System Programmable SuperFAST High Density PLD Functional Block Diagram • SUPERFAST HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 6000 PLD Gates — 128 I/O Pins, Eight Dedicated Inputs — 128 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address D |
|
|
|
|
Lattice Semiconductor |
In-System Programmable Power Supply Monitoring and Margining Controller ■ Power Supply Margin and Trim Functions • • • • Trim and margin up to six power supplies Dynamic voltage control through I2C Four hardware selectable voltage profiles Independent Digital Closed-Loop Trim function for each output Application Block Di |
|
|
|
|
Lattice Semiconductor |
Super Fast High Density PLDs ■ High Performance ■ Broad Device Offering • fMAX = 400MHz maximum operating frequency • tPD = 2.5ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output • Multiple temperature range s |
|
|
|
|
Lattice Semiconductor |
High Performance E2CMOS PLD Generic Array Logic • HIGH PERFORMANCE E2CMOS® TECHNOLOGY — 3.5 ns Maximum Propagation Delay — Fmax = 250 MHz — 3.0 ns Maximum from Clock Input to Data Output — UltraMOS® Advanced CMOS Technology • 50% to 75% REDUCTION IN POWER FROM BIPOLAR — 75mA Typ Icc on Low Power D |
|
|
|
|
Lattice Semiconductor |
Zero Power E2CMOS PLD • ZERO POWER E2CMOS TECHNOLOGY — 100µA Standby Current — Input Transition Detection on GAL16V8Z — Dedicated Power-down Pin on GAL16V8ZD — Input and Output Latching During Power Down • HIGH PERFORMANCE E2CMOS TECHNOLOGY — 12 ns Maximum Propagation Del |
|
|
|
|
Lattice Semiconductor |
In-System Programmable High Density PLD • HIGH-DENSITY PROGRAMMABLE LOGIC — 128 I/O Pins — 11000 PLD Gates — 384 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH-PERFORM |
|
|
|
|
Lattice Semiconductor |
In-System Programmable Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — Three Device Options: 80 to 160 Programmable I/O Pins — “Any Input t |
|
|
|
|
Lattice Semiconductor |
In-System Programmable High Density PLD • HIGH-DENSITY PROGRAMMABLE LOGIC — 2000 PLD Gates — 32 I/O Pins, Four Dedicated Inputs — 96 Registers — High-Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random |
|
|
|
|
Lattice Semiconductor |
High-Performance EE CMOS Programmable Logic x High-performance electrically-erasable CMOS PLD families x 32 to 128 macrocells x 44 to 100 pins in cost-effective PLCC, PQFP and TQFP packages x SpeedLocking™ – guaranteed fixed timing up to 16 product terms x Commercial 5/5.5/6/7.5/10/12/15-ns tPD |
|
|
|
|
Lattice Semiconductor |
(OR3xxx) 3C and 3T Field-Programmable Gate Arrays ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance, cost-effective, 0.35 µm (OR3C) and 0.3 µm (OR3T) 4-level metal technology, (4- or 5-input look-up table delay of 1.1 ns with -7 speed grade in 0.3 µm). Same basic architecture as lower-voltage, advanc |
|
|
|
|
Lattice Semiconductor |
Super Fast High Density PLDs ■ High Performance ■ Broad Device Offering • fMAX = 400MHz maximum operating frequency • tPD = 2.5ns propagation delay • Up to four global clock pins with programmable clock polarity control • Up to 80 PTs per output • Multiple temperature range s |
|
|
|
|
Lattice Semiconductor |
3.3V In-System Programmable SuperBIG High Density PLD • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 60,000 PLD Gates/1080 Macrocells — 192-360 I/O Pins Supporting 3.3V/2.5V I/O — 1440 Registers — High-Speed Global and Big Fast Megablock (BFM) Interconnect — Wide 20-Macrocell |
|
|
|
|
Lattice Semiconductor |
3.3V In-System Programmable SuperBIG High Density PLD • SuperBIG HIGH DENSITY IN-SYSTEM PROGRAMMABLE LOGIC — 3.3V Power Supply — 32,000 PLD Gates/600 Macrocells — 192-264 I/O Pins Supporting 3.3V/2.5V I/O — 864 Registers — High-Speed Global and Big Fast Megablock (BFM) Interconnect — Wide 20-Macrocell G |
|
|
|
|
Lattice Semiconductor |
In-System Programmable 3.3V Generic Digital CrosspointTM • IN-SYSTEM PROGRAMMABLE GENERIC DIGITAL CROSSPOINT FAMILY — Advanced Architecture Addresses Programmable PCB Interconnect, Bus Interface Integration and Jumper/Switch Replacement — “Any Input to Any Output” Routing — Fixed HIGH or LOW Output Option |
|
|
|
|
Lattice Semiconductor |
High Density Programmable Logic |
|
|
|
|
Lattice Semiconductor |
In-System Programmable High Density PLD • HIGH-DENSITY PROGRAMMABLE LOGIC — 256 I/O Pins — 12000 PLD Gates — 512 Registers — High Speed Global Interconnect — Wide Input Gating for Fast Counters, State Machines, Address Decoders, etc. — Small Logic Block Size for Random Logic • HIGH PERFORM |
|