| No. | Partie # | Fabricant | Description | Fiche Technique |
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JRC |
Audio Processor |
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JRC |
Audio Processor h Operating Voltage 8 to 10V h Internal 4 Input Audio Selectors and Monitor Output hLow Noise VCA hNJRC Surround "eala" hSimulated Stereo 2 hVariable AGC Compression Level via I C (4-levels) hBi-CMOS Technology hPackage Outline SSOP32 sBLOCK DIAGRA |
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JRC |
Passive Matrix Surround Circuit / DMP20 q Operating Voltage 7.5 to 13V 2 q I C BUS Interface q Passive Matrix Surround Circuit q Trimmer & BPF for Center Channel q Trimmer & LPF for Subwoofer Channel q Trimmer & Simulated Stereo Function for Surround Channel q Bi-CMOS Technology q Package |
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JRC |
Lithium-Battery Charger Controller IC with Timer / DMP20 / SSOP20 it has over voltage, over discharge, temperature detection, and a charge over timer. Also, the adaptor and the charge control circuit are mounted on one chip. ■FEATURES ● Charge Control Feedback by Photocoupler ● Adjustable Charge Voltage ● Adjustabl |
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JRC |
Electronic Volume / SSOP32 ●Operating Voltage 7.5 to 13V 2 ●I C BUS Interface ●Low Output Noise -103dBVtyp ●Low Distortion 0.005%typ ●3ch Stereo & 1ch Monaural Input Selector ●Tone Control Bass / Treble ●Main Volume ●Balance & Fader ●Bi-CMOS Technology ●Package Outline SSOP32 |
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JRC |
Lithium-ion Battery Charger Controller with Timer / SSOP20 for safety conscious design: Over voltage, Over discharge, temperature monitor and over charge timers. ■PACKAGE OUTLINE NJW4108V ■FEATURES ● Adjustable Charge Voltage ● Adjustable Pre-Charge and Full Charge Current ● Temperature Monitor ● Over Char |
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JRC |
Electronic Volume q Operating Voltage 2 q I C Bus control q Slave Address Selector q Volume (VCA type) q 2 Auxiliary Port q Bi-CMOS Technology q Package Outline 7.5 to 13V available for using two chips on same serial bus line 0 to –100dB/0.5dBstep, MUTE DMP20, DIP20 |
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JRC |
Signal Processor for TFT Display / QFP64-G1 q Supply Voltage 5V q Y/C Separator Input q NTSC/PAL System (3.58MHz, 4.43MHz) q Unnecessary Adjustment of Oscillation Frequency for Internal Count Down Circuit. q External One System Input for Analog RGB q Internal Enhancer Circuit q Internal GAMMA |
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JRC |
Stepper Motor / DIP16 / EMP16-E2 • Wide Voltage Range 5 to 50V • Low RON=0.9Ω typ.@Io=±500mA(U&L) • STEP & DIR input Operation • Half / Full Step Operation • RESET Function • Output Power Save Function (INH) • Motor Origin Monitor Output (MO) • Thermal Shutdown Circuit • BCD Process |
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JRC |
Vopr1 5V /Vopr2 9V / SSOP24-E1 q Operating Voltage q Internal Oscillator Circuit q Rise Time / Fall Time q Maximum Output Current q Bi-CMOS Technology q Package Outline sPIN CONFIGURATION sPACKAGE OUTLINE NJW4710VE1 Vcc1=4.5V to 5.5V, Vcc2=8.0 to 10.0V 200MHz to 500MHz 0.8ns typ |
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JRC |
2.7V-5.5V / SSOP14 low operating voltage(2.7V) and can be full-swing outputted regardless of supply voltage. s PACKAGE OUTLINE NJW5211V The small package(SSOP14) is suitable for portable applications. s FEATURES q Low Operating Voltage 2.7 to 5.5V q 8bit 8ch D/A Conv |
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JRC |
Phase Shifter-less Wide Band FM IF Demodulator IC ● Unnecessary External phase shifter (CD or IFT) ● Auto IF detection IF = 1.5MHz to 15MHz * S-curve characteristic cannot be obtained ● Demodulated Output Frequency Range fmod = 20Hz to 100kHz * External parts modification : up to 300kHz ● Ex |
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JRC |
Electronic Volume q Operating Voltage q Three-Wired Serial Data Control q Chip Selector q Volume q Bi-CMOS Technology q Package Outline s BLOCK DIAGRAM ±4.5 to ±7.5V available for using four chips on same serial bus line. 0 to -95dB/1dBstep, MUTE SSOP16, DMP16, DIP16 |
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JRC |
3-Band Tone Control IC • Operating Voltage • 3-Wired Serial Control • Low Total Harmonic Distortion • Low Output Noise • Tone Control • Bi-CMOS Technology • Package Outline • Mute Function 4.5 to 7.5V Chip Address Select Function 0.0002% typ. @Tone=OFF -120dB typ. @Tone |
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JRC |
Audio Processor / SDIP32 q Operating Voltage 7.5 to 13V q 6ch Input Selector q Tone Control Bass / Treble q eala(NJRC Original Surround System) q Simulated Stereo q Voice Enhancement System 2 q I C BUS Interface q Bi-CMOS Technology q Package Outline SDIP32 s BLOCK DIAGRAM |
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JRC |
Signal Processor for TFT Display / QFP64-K1 qInternal Y/C separator circuit qNTSC matching for Composite qInternal one systems input for analog RGB for NTSC/PAL qInternal count down circuit at H,V qInternal enhancer circuit qInternal Side black control circuit qInternal PWM control circuit qIn |
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JRC |
Video Switch / QFP48-P1 q Operating Voltage 9.0V q 4-input 3-output 3-Circuits (Y, Pb, and Pr signal) q Wide frequency range 0dB at 50MHz typ. q Internal 6dB amplifier (Selectable Bypass or 6dB) q External logic discernment terminal q External logic control terminal q Selec |
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JRC |
Video Switch / SSOP32 q Operating Voltage 4.5 to 5.5V 2 q I C BUS Interface q 5-input 1-output video switch q 3-input 1-output 2-circuit video switch q 6th order Low Pass Filter q Internal synchronous separation circuit q Internal synchronous signal detection circuit q Po |
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JRC |
PLL Synthesizer Operating Voltage 5V Low Operating Current 15mA typ. @Vcc=5V Prescaler accepts frequencies up to 1GHz on chip Reference Signal Oscillator with peripheral of Xtal on chip 34V max. tuning voltage output Package Outline SSOP16 PACKAGE OUTLINE |
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JRC |
Parallel Input 8-channel Sink Driver ●8-channel Parallel Input Parallel Output ●Built-in Flip-Flops for latching Input data ●Supply Voltage ●Output Voltage VDD=4.0 to 5.5V VDS=up to 40V (45V Rating) ●Output Current 300mA(DC) / ch. 600mA(Peak) / ch. ●Built-in Noise Filter (CLRb P |
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