| No. | Partie # | Fabricant | Description | Fiche Technique |
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Intersil Corporation |
Two Dimensional Convolver • Single Chip 3 x 3 Kernel Convolution • Programmable On-Chip Row Buffers • DC to 32MHz Clock Rate • Cascadable for Larger Kernels and Images • On-Chip 8-Bit ALU • Dual Coefficient Mask Registers, Switchable in a Single Clock Cycle • 8-Bit Signed or U |
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Intersil Corporation |
HSP45116 • NCO and CMAC on One Chip • 15MHz, 25.6MHz, 33MHz Versions • 32-Bit Frequency Control • 16-Bit Phase Modulation • 16-Bit CMAC • 0.008Hz Tuning Resolution at 33MHz • Spurious Frequency Components < -90dBc • Fully Static CMOS Applications • Frequency |
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Intersil Corporation |
Numerically Controlled Oscillator/ Modulator • NCO and CMAC on One Chip • 52MHz Version • 32-Bit Frequency Control • 16-Bit Phase Modulation • 16-Bit CMAC • 0.013Hz Tuning Resolution at 52MHz • Programmable Rounding Option • Spurious Frequency Components < -90dBc • Fully Static CMOS Applicatio |
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Intersil Corporation |
CommLinkTM Direct Digital Synthesizer • 125MSPS Output Sample Rate with 5V Digital Supply • 100MSPS Output Sample Rate with 3.3V Digital Supply • 14-bit DAC with Internal Reference • Parallel Control Interface for Fast Tuning (50MSPS Control Register Write Rate) • 48-bit Programmable Fre |
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Intersil Corporation |
Dual FIR Filter • Two Independent 8-Tap FIR Filters Configurable as a Single 16-Tap FIR • 10-Bit Data and Coefficients • On-Board Storage for 32 Programmable Coefficient Sets • Up To: 256 FIR Taps, 16 x 16 2-D Kernels, or 10 x 19-Bit Data and Coefficients • Programmabl |
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Intersil Corporation |
Histogrammer/Accumulating Buffer • 10-Bit Pixel Data • 4k x 4k Frame Sizes • Asynchronous Flash Clear Pin • Single Cycle Memory Clear • Fully Asynchronous 16 or 24-Bit Host Interface • Generates and Stores Cumulative Distribution Function • Look Up Table Mode • 1024 x 24-Bit Delay M |
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Intersil Corporation |
Digital Costas Loop • Clock Rates Up to 52MHz • Selectable Matched Filtering with Root Raised Cosine or Integrate and Dump Filter • Second Order Carrier and Symbol Tracking Loop Filters • Automatic Gain Control (AGC) • Discriminator for FM/FSK Detection and Discriminato |
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Intersil Corporation |
Multilevel Pipeline Registers • Four 8-Bit Registers • Hold, Transfer and Load Instructions • Single 4-Stage or Dual-2 Stage Pipelining • All Register Contents Available at Output • Fully TTL Compatible • Three-State Outputs • High Speed, Low Power CMOS Applications • Array Proc |
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Intersil Corporation |
Serial I/O Filter • 45MHz Clock Rate • 256 Tap Programmable FIR Filter • 24-Bit Data, 32-Bit Coefficients • Cascade of up to 5 Half Band Filters • Decimation from 1 to 256 • Two Pin Interface for Down Conversion by FS/4 • Multiplier for Mixing or Scaling Input with an |
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Intersil Corporation |
Decimating Digital Filter • Single Chip Narrow Band Filter with up to 96dB Attenuation • DC to 33MHz Clock Rate • 16-Bit 2’s Complement Input • 20-Bit Coefficients in FIR • 24-Bit Extended Precision Output • Programmable Decimation up to a Maximum of 16,384 • Standard 16-Bit M |
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Intersil Corporation |
16-Bit Numerically Controlled Oscillator • 25.6MHz, 33MHz Versions • 32-Bit Center and Offset Frequency Control • 16-Bit Phase Control • 8 Level PSK Supported Through Three Pin Interface • Simultaneous 16-Bit Sine and Cosine Outputs • Output in Two’s Complement or Offset Binary • <0.008Hz T |
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Intersil Corporation |
Numerically Controlled Oscillator/Modulator • NCO and CMAC on One Chip • 15MHz, 25.6MHz, 33MHz Versions • 32-Bit Frequency Control • 16-Bit Phase Modulation • 16-Bit CMAC • 0.008Hz Tuning Resolution at 33MHz • Spurious Frequency Components < -90dBc • Fully Static CMOS Applications • Frequency |
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Intersil Corporation |
Address Sequencer • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Block Oriented 24-Bit Sequencer • Configurable as Two Independent 12-Bit Sequencers • 24 x 24 Crosspoint Switch • Programmable D |
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Intersil Corporation |
Address Sequencer • This Circuit is Processed in Accordance to MIL-STD883 and is Fully Conformant Under the Provisions of Paragraph 1.2.1. • Block Oriented 24-Bit Sequencer • Configurable as Two Independent 12-Bit Sequencers • 24 x 24 Crosspoint Switch • Programmable D |
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Intersil Corporation |
Binary Correlator • Reconfigurable 256 Stage Binary Correlator • 1-Bit Reference x 1, 2, 4, or 8-Bit Data • Separate Control and Reference Interfaces • 25.6, 33MHz Versions • Configurable for 1-D and 2-D Operation • Double Buffered Mask and Reference • Programmable Outp |
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Intersil Corporation |
Digital Video Mixer • 12-Bit Pixel Data • Two’s Complement or Unsigned Data • 12-Bit Mix Factor • 13-Bit Signed or Unsigned Three State Output • Overflow Detection and Output Saturation • Rounding to 8, 10, 12, or 13-Bits • Input and Output Pixel Data Synchronous to Cloc |
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Intersil Corporation |
3 x 3 Image Filter • DC to 30MHz Clock Rate • Configurable for 1-D and 2-D Correlation/Convolution • Dual Coefficient Mask Registers, Switchable in a Single Clock Cycle • Two’s Complement or Unsigned 8-Bit Input Data and Coefficients • 20-Bit Extended Precision Output • S |
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Intersil Corporation |
Digital Down Converter • 75 MSPS Input Data Rate • 16-Bit Data Input; Offset Binary or 2’s Complement Format • Spurious Free Dynamic Range Through Modulator >102dB • Frequency Selectivity: <0.006Hz • Identical Lowpass Filters for I and Q • Passband Ripple: <0.04dB • Stopba |
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Intersil Corporation |
Digital Quadrature Tuner • Input Sample Rates to 52 MSPS • Internal AGC Loop for Output Level Stability • Parallel or Serial Output Data Formats • 10-Bit Real or Complex Inputs • Bidirectional 8-Bit Microprocessor Interface • Frequency Selectivity <0.013Hz • Low Pass Filter |
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Intersil Corporation |
Programmable Downconverter • Up to 65 MSPS Front-End Processing Rates (CLKIN) and 55 MSPS (41 MSPS Using the Discriminator) Back-End Processing Rates (PROCCLK) Clocks May Be Asynchronous • Processing Capable of >100dB SFDR • Up to 255-Tap Programmable FIR • Overall Decimation |
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