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Integral |
8-Bit Bidirectional Universal Shift Register with Parallel I/O High-Speed Silicon-Gate CMOS a multiplexed parallel input/output data port to achieve full 8-bit handling in a 20 pin package. Due to the large output drive capability and the 3-state feature, this device is ideally suited for interface with bus lines in a bus-oriented system. T |
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Integral |
Quad 2-Input Date Selector/Multiplexer with 3-State Outputs High-Speed Silicon-Gate CMOS 8 = GND Select X L H Outputs Y0-Y3 Z A0-A3 B0-B3 X=don’t care Z = high-impedance state A0-A3,B0-B3=the levels of the respective Nibble Inputs 356 IN74AC257 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Volta |
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Integral |
Octal 3-State Noninverting Bus Transceiver |
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Integral |
Octal 3-State Noninverting Buffer/Line Driver/Line Receiver High-Speed Silicon-Gate CMOS uts YA,YB L H Z 318 IN74AC244 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD Tstg TL * Parameter DC Supply Voltage (Referenced to GND) DC Input Voltage (Referenced to GND) DC Output Voltage (Referenced to GND) DC Input Current, per Pin DC O |
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Integral |
Octal 3-State Noninverting Bus Transceiver |
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Integral |
Octal 3-State Noninverting Bus Transceiver High-Speed Silicon-Gate CMOS on L Operation Data Transmitted from Bus B to Bus A Data Transmitted from Bus A to Bus B Buses Isolated (High Impedance State) PIN 20=VCC PIN 10 = GND L H H X X = don’t care 326 IN74AC245 MAXIMUM RATINGS* Symbol VCC VIN VOUT IIN IOUT ICC PD |
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Integral |
LCD driver 9 SCL 38 Vs 37 A0/OS 36 A1 35 VDD 34 A2/BP 33 BP1 32 S1 31 S2 30 S3 29 S4 28 S5 27 S6 26 S7 25 S8 24 S9 23 S10 22 S11 21 S12 Рисунок 2 - Обозначение выводов в корпусе 1 INF8574AN Таблица 1 - Предельные и предельно допустимые режимы Наименование |
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