| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|
|
|
|
Infineon |
256Mb (32MB) HYPER FLASH • 3.0 V I/O, 11 bus signals - Single ended clock • 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#) • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Read-write data strobe (RWDS) - HYPERFLASH™ memories use RWDS only as a Read Data Strobe • Up |
|
|
|
|
Infineon |
128Mb (16MB) HYPER FLASH • 3.0 V I/O, 11 bus signals - Single ended clock • 1.8 V I/O, 12 bus signals - Differential clock (CK, CK#) • Chip Select (CS#) • 8-bit data bus (DQ[7:0]) • Read-write data strobe (RWDS) - HYPERFLASH™ memories use RWDS only as a Read Data Strobe • Up |
|
|
|
|
Infineon |
Automotive PSoC 4100S Plus MCU • Automotive Electronics Council (AEC) AEC-Q100 Qualified • 32-bit MCU subsystem - 48-MHz Arm® Cortex®-M0+ CPU - Up to 128 KB of flash with Read Accelerator - Up to 16 KB of SRAM - 8-channel DMA engine • Programmable analog - Two opamps with reconfig |
|