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IDT |
5-output 1.8V HCSL Fanout Buffer |
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IDT |
Four Output Differential Fanout Buffer Benefits: • • Low power differential fanout buffer for PCIExpress and CPU clocks 20-pin MLF or TSSOP packaging Output Features: • • 4 - low power differential output pairs Individual OE# control of each output pair General Description: The ICS9DBL4 |
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IDT |
Clock Buffer • 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs w/Zo=100 Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF phase jitter is PCIe Gen1-2-3 compliant • DIF additive phase jitter <300fs rms for SGMII Block Diagra |
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IDT |
EIGHT OUTPUT DIFFERENTIAL BUFFER • 8 - 0.7V current-mode differential HCSL output pairs • Supports zero delay buffer mode and fanout mode • Selectable bandwidth • 50-110 MHz operation in PLL mode • 5-166 MHz operation in Bypass mode Features/Benefits • 3 Selectable SMBus Addresses; |
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IDT |
4-Output 3.3V PCIe Zero-delay Buffer • 4 – 1-200 MHz Low-Power (LP) HCSL DIF pairs • 9DBL0442 default ZOUT = 100 • 9DBL0452 default ZOUT = 85 • 9DBL04P2 factory programmable defaults • Easy AC-coupling to other logic families, see IDT application note AN-891 Key Specifications • PCIe |
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IDT |
8 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB • 8 – 1-167MHz Low-Power (LP) HCSL DIF pairs w/ZO=100 Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew < 80ps • DIF phase jitter is PCIe Gen1-2-3 compliant • Very low additive phase jitter in bypass mode Block Diagram |
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IDT |
9-Output 3.3V PCIe Fanout Buffer • 9 – 1-200 MHz Low-Power (LP) HCSL DIF pairs • 9DBL0941 default Zout = 100Ω • 9DBL0951 default Zout = 85Ω • 9DBL09P1 factory programmable defaults • Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications • DIF |
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IDT |
6 O/P 1.5V PCIe Gen1-2-3 ZDB/FOB • 6 – 1-167MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <60ps • DIF phase jitter is PCIe Gen1-2-3 compliant • DIF bypass mode additive phase jitter is <300fs rms for PCIe Gen3 • DI |
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IDT |
5-Output 1.5V PCIe Gen1-2-3 Fanout Buffer • 5 - 1-167MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF output-to-output skew <60ps • DIF additive phase jitter is <300fs rms for PCIe Gen3 • DIF additive phase jitter <350s rms for SGMII Featu |
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IDT |
Six Output Differential Buffer Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low |
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IDT |
Two Output Differential Buffer Benefits: • OE# pins/Suitable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter peaking in downstream PLL's • Spread Spectrum Compatible/tracks spreading input clock for low |
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IDT |
6-output 1.8V PCIe Gen1-2-3 ZDB/FOB • 6 - 1-200 MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF additive cycle-to-cycle jitter <5ps • DIF output-to-output skew <60ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms for SGMII Bloc |
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IDT |
2-output 1.8V PCIe Gen1/2/3 Zero Delay / Fanout Buffer • 2 – 1-200MHz Low-Power (LP) HCSL DIF pairs Key Specifications • DIF cycle-to-cycle jitter <50ps • DIF output-to-output skew <50ps • DIF additive phase jitter is <100fs rms for PCIe Gen3 • DIF additive phase jitter <300fs rms (12k-20MHz) Block Diagr |
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IDT |
8-output 3.3V PCIe Zero-Delay Buffer |
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IDT |
Two Output Differential Buffer • 2 - 0.7V current mode differential output pairs (HCSL) Features/Benefits • CLKREQ# pin for outputs 1 and 4/output enable for Express Card applications • PLL or bypass mode/PLL can dejitter incoming clock • Selectable PLL bandwidth/minimizes jitter |
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IDT |
Six Output Differential Buffer Benefits The 9DB106 zero-delay buffer supports PCIe Gen1 and Gen2 clocking requirements. The 9DB106 is driven by a differential SRC output pair from an IDT CK410/CK505-compliant main clock generator. It attenuates jitter on the input clock and has a |
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IDT |
PCI Express Jitter Attenuator |
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IDT |
2-Output 3.3V LP-HCSL Zero-Delay Buffer ▪ Loss Of Signal (LOS) open drain output ▪ 2 1 –200 MHz Low-Power (LP) HCSL DIF pairs — 9DBL0243 default Zout = 100Ω — 9DBL0253 default Zout = 85Ω ▪ Easy AC-coupling to other logic families; see IDT application note AN-891. Key Specifications ▪ PCIe G |
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IDT |
8-output 3.3V LP-HCSL Zero-Delay Buffer ▪ Loss Of Signal (LOS) open drain output ▪ 8 – 1-200 MHz Low-Power (LP) HCSL DIF pairs ▪ 9DBL0843 default Zout = 100Ω ▪ 9DBL0853 default Zout = 85Ω ▪ Easy AC-coupling to other logic families, see IDT application note AN-891. Key Specifications ▪ PCIe |
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IDT |
PCIe Gen1-5 Clock Fanout Buffers to aid robust designs. Flexible Power Sequencing (FPS) ensures well-defined behavior under various power up scenarios, while Power Down Tolerant (PDT) ESD protection on all input pins allows input pins to be driven before VDD is applied. The 9DBL0255 |
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