| No. | Partie # | Fabricant | Description | Fiche Technique |
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IDT |
1:2 LVCMOS/LVTTL-to-LVCMOS/LVTTL Zero Delay Buffer • Third generation FemtoClock® technology • Low phase noise zero delay buffer • Low skew outputs • One LVCMOS/LVTTL clock input • Two LVCMOS/LVTTL outputs • Phase noise: -125dBc/Hz @1kHz offset; -130dBc/Hz @100kHz offset • Cycle-to-cycle jitter: 60ps |
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IDT |
1-TO-8 DIFFERENTIAL-TO-LVCMOS/LVTTL CLOCK GENERATOR • Eight LVCMOS/LVTTL outputs (2 banks of 4 outputs) • Selectable differential CLK1, nCLK1 or LVCMOS clock input • CLK1, nCLK1 pair can accept the following differential input levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL • CLK0 supports the following inpu |
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IDT |
Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator |
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IDT |
Differential-to-LVCMOS/LVTTL Zero Delay Clock Generator |
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IDT |
Differential-to-LVCMOS/LVTTL Clock Generator |
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Panasonic Semiconductor |
Wide bandwidth analog switch • Supporting TVs with a BS tuner • 4 channels of S-input • Audio muting circuit built-in • Oscillation preventing circuit built-in • Black and white, or color switchng function built-in 36.8±0.3 0.96±0.25 3.3±0.25 s Applications • TV 3° to 15° S |
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Panasonic Semiconductor |
Wide bandwidth analog switch • 2-input 1-output circuit (DC switch type) • Built-in 6 dB amplifier for RGB signal (1.5 dB for 75 Ω termination) • Built-in sync. separation circuit (Supporting sync. on green and power save) • Higher speed horizontal / vertical sync. signal circui |
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