| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Integrated Device Technology |
3.3V Synchronous ZBT SRAMs 2.5V I/O Description The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given th |
|
|
|
|
IDT |
3.3V CMOS Static RAM 1 Meg (128K x 8-Bit) Center Power & Ground Pinout ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and o |
|
|
|
|
Integrated Device Technology |
3.3V Synchronous ZBT SRAMs 2.5V I/O Description The IDT71V2556/58 are 3.3V high-speed 4,718,592-bit (4.5 Megabit) synchronous SRAMS. They are designed to eliminate dead bus cycles when turning the bus around between reads and writes, or writes and reads. Thus, they have been given th |
|
|
|
|
Integrated Device Technology |
LOW POWER 3.3V CMOS FAST SRAM 256K • Ideal for high-performance processor secondary cache • Commercial (0° to 70°C) and Industrial (-40° to 85°C) temperature options • Fast access times: — Commercial: 10/12/15/20ns — Industrial: 15ns • Low standby current (maximum): — 2mA full standby |
|
|
|
|
Integrated Device Technology |
(IDT71V416VL/VS) 3.3V CMOS Static RAM 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. ◆ Equal access and cycle times – Commercial and Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Bidirectional data inputs and outpu |
|
|
|
|
Renesas |
3.3V CMOS Static RAM ◆ 128K x 8 advanced high-speed CMOS static RAM ◆ JEDEC revolutionary pinout (center power/GND) for reduced noise ◆ Equal access and cycle times – Commercial: 10/12/15ns – Industrial: 12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Inputs and o |
|
|
|
|
Renesas |
3.3V CMOS Static RAM ◆ 512K x 8 advanced high-speed CMOS Static RAM ◆ JEDEC Center Power / GND pinout for reduced noise ◆ Equal access and cycle times — Commercial and Industrial: 10/12/15ns ◆ Single 3.3V power supply ◆ One Chip Select plus one Output Enable pin ◆ Bidire |
|
|
|
|
Renesas |
3.3V CMOS Static RAM ◆ 256K x 16 advanced high-speed CMOS Static RAM ◆ JEDEC Center Power / GND pinout for reduced noise. ◆ Equal access and cycle times – Commercial and Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Bidirectional data inputs and o |
|
|
|
|
IDT |
3.3V CMOS Static RAM Description ◆ 64K x 16 advanced high-speed CMOS Static RAM The IDT71V016 is a 1,048,576-bit high-speed Static RAM ◆ Commercial (0° to +70°C) and Industrial ( –40°C to +85°C) organized as 64K x 16. It is fabricated using IDT’s high-perfomance, ◆ E |
|
|
|
|
IDT |
3.3V Synchronous ZBT SRAM ◆ 128K x 36 memory configurations ◆ Supports high performance system speed - 150 MHz (3.8 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the need to co |
|
|
|
|
Integrated Device Technology |
HIGH-SPEED 3.3V 2K x 8 DUAL-PORT STATIC RAM • High-speed access —Commercial: 25/35/55ns (max.) • Low-power operation —IDT71V321S —Active: 250mW (typ.) —Standby: 3.3mW (typ.) —IDT71V321L —Active: 250mW (typ.) —Standby: 660µW (typ.) • Two INT flags for port-to-port communications • On-chip port |
|
|
|
|
Integrated Device Technology |
3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT) • 512K x 8 advanced high-speed CMOS Static RAM • JEDEC Center Power / GND pinout for reduced noise • Equal access and cycle times — 12/15/20ns • Single 3.3V power supply • One Chip Select plus one Output Enable pin • Bidirectional data inputs and ou |
|
|
|
|
Integrated Device Technology |
3.3V Synchronous SRAMs 256K x 36, 512K x 18 memory configurations Supports high system speed: – 166MHz 3.5ns clock access time – 150MHz 3.8ns clock access time – 133MHz 4.2ns clock access time LBO input selects interleaved or linear burst mode Self-timed write cycle with g |
|
|
|
|
IDT |
3.3V Synchronous SRAMs x x x x x x x x 256K x 36, 512K x 18 memory configurations Supports fast access times: – 7.5ns up to 117MHz clock frequency – 8.0ns up to 100MHz clock frequency – 8.5ns up to 87MHz clock frequency LBO input selects interleaved or linear burst mode |
|
|
|
|
Integrated Device Technology |
3.3V CMOS Static RAM 256K x 16 advanced high-speed CMOS Static RAM JEDEC Center Power / GND pinout for reduced noise. ◆ Equal access and cycle times – Commercial and Industrial: 10/12/15ns ◆ One Chip Select plus one Output Enable pin ◆ Bidirectional data inputs and outpu |
|
|
|
|
IDT |
3.3V Synchronous ZBT SRAMs ◆ 128K x 36, 256K x 18 memory configurations ◆ Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) ◆ ZBTTM Feature - No dead cycles between write and read cycles ◆ Internally synchronized output buffer enable eliminates the |
|
|
|
|
IDT |
3.3V Synchronous ZBT SRAMs x 256K x 36, 512K x 18 memory configurations x Supports high performance system speed - 100 MHz (7.5 ns Clock-to-Data Access) x ZBTTM Feature - No dead cycles between write and read cycles x Internally synchronized output buffer enable eliminates the |
|
|
|
|
Integrated Device Technology |
3.3V CMOS Static RAM 1 Meg (64K x 16-Bit) x x IDT71V016SA Description The IDT71V016 is a 1,048,576-bit high-speed Static RAM organized as 64K x 16. It is fabricated using IDT’s high-perfomance, high-reliability CMOS technology. This state-of-the-art technology, combined with innovative cir |
|
|
|
|
Integrated Device Technology |
3.3V CMOS FAST SRAM WITH 2.5V COMPATIBLE INPUTS 256K (32K x 8-BIT) • Ideal for high-performance processor secondary cache • Fast access times: — 12/15/20ns • Inputs are 2.5V and LVTTL compatible: VIH = 1.8V • Outputs are LVTTL compatible • Low standby current (maximum): — 2mA full standby • Small packages for space- |
|
|
|
|
Integrated Device Technology |
3.3V Synchronous ZBT SRAMs 128K x 36, 256K x 18 memory configurations Supports high performance system speed - 200 MHz (3.2 ns Clock-to-Data Access) ZBTTM Feature - No dead cycles between write and read cycles Internally synchronized output buffer enable eliminates the need to |
|