Hynix Semiconductor HMT fiche technique

No.	Partie #	Fabricant	Description
1	HMT451S6BFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500 • Bi-direct
2	HMT125U7BFR8C	Hynix Semiconductor	240pin DDR3 SDRAM Unbuffered DIMMs and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 51
3	HMT151R7AFP8C	Hynix Semiconductor	DDR3 SDRAM Registered DIMM and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Key Parameters 1.3 Speed Grade 1.4 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1
4	HMT351R7AFR8A	Hynix Semiconductor	240pin DDR3 SDRAM Registered DIMM • • • • • • • • • • • • • Power Supply: VDD=1.35V (1.283V to 1.45V) VDDQ = 1.35V (1.283V to 1.45V) Backward Compatible with 1.5V DDR3 Memory Module VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal bank
5	HMT41GS6AFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500 • Bi-directional
6	HMT351U7BFR8C	Hynix Semiconductor	240pin DDR3 SDRAM Unbeffered DIMM • VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.6V • Functionality and operations comply with the DDR3 SDRAM datasheet • 8 internal banks • Data transfer rates: PC3-10600, PC3-8500, or PC3-6400 • Bi-directional Differential Data Strob
7	HMT351S6BFR8A	Hynix Semiconductor	204pin DDR3 SDRAM SODIMM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Functionality and operations comply with the DDR3 SDRAM datasheet • 8 internal banks • Data transfer rates: PC3-10600, PC3-8500, or PC3-6400 • Bi-dir
8	HMT351S6EFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates:PC3-12800,
9	HMT112U6AFP8C	Hynix Semiconductor	240pin DDR3 SDRAM Unbuffered DIMMs and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 51
10	HMT125U7AFR8C	Hynix Semiconductor	240pin DDR3 SDRAM Unbuffered DIMMs and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 51
11	HMT425U6AFR6A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ=1.35V (1.283 to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-12800, PC3-10600, PC3-8500 • Bi-directional Differential
12	HMT325R7BFR8C	Hynix Semiconductor	DDR3 SDRAM Registered DIMM • • • • • • • • • • • • Power Supply: VDD=1.5V (1.425V to 1.575V) VDDQ = 1.5V (1.425V to 1.575V) VDDSPD=3.0V to 3.6V Functionality and operations comply with the DDR3L SDRAM datasheet 8 internal banks Data transfer rates: PC3-10600, PC3-8500 Bi-Direc
13	HMT451S6MMP8C	Hynix Semiconductor	DDR3 SDRAM and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 4G
14	HMT425S6AFR6A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500 • Bi-directional
15	HMT451S6AFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500 • Bi-directional
16	HMT451S6AFR8C	Hynix Semiconductor	DDR3 SDRAM • VDD=1.5V +/- 0.075V • VDDQ=1.5V +/- 0.075V • VDDSPD=3.0V to 3.6V • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600,PC3-8600 • Bi-directional Differential Data Strobe • 8 bit pre-fetch • Burst Length (BL) switch on-the-fly: B
17	HMT112U7BFR8C	Hynix Semiconductor	240pin DDR3 SDRAM Unbuffered DIMMs and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Speed Grade & Key Parameters 1.3 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1 51
18	HMT325S6EFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates:PC3-12800,
19	HMT41GS6BFR8A	Hynix Semiconductor	DDR3L SDRAM • Power Supply: VDD=1.35V (1.283V to 1.45V) • VDDQ = 1.35V (1.283V to 1.45V) • VDDSPD=3.0V to 3.6V • Backward Compatible with 1.5V DDR3 Memory module • 8 internal banks • Data transfer rates: PC3-14900, PC3-12800, PC3-10600, PC3-8500 • Bi-direct
20	HMT31GR7AMP4C	Hynix Semiconductor	DDR3 SDRAM Registered DIMM and Ordering Information 1.1.1 Features 1.1.2 Ordering Information 1.2 Key Parameters 1.3 Speed Grade 1.4 Address Table 2. Pin Architecture 2.1 Pin Definition 2.2 Input/Output Functional Description 2.3 Pin Assignment 3. Functional Block Diagram 3.1