Hynix Semiconductor HC2 fiche technique

No.	Partie #	Fabricant	Description
1	HC2510	Hynix Semiconductor	Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network
2	HC2509C	Hynix Semiconductor	Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Five and One Bank of Four Outputs N
3	HC2510C	Hynix Semiconductor	Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications l l l l l l l l l l l Phase-Locked Loop Clock Distribution for Synchronous DRAM Applications Supports PC-100 and Meets “PC100 SDRAM registered DIMM Specification Rev. 1.2” Distributes One Clock Input to One Bank of Ten Outputs No External RC Network
4	GD74HC244	Hynix Semiconductor	Octal Noninverting 3-State Buffers
5	GD74HC245	Hynix Semiconductor	Octal Noninverting 3-State Transceivers