No. | Partie # | Fabricant | Description | Fiche Technique |
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Freescale Semiconductor |
Dual Core Digital Signal Processor 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or periphera |
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Freescale Semiconductor |
Six-Core Digital Signal Processor tial). • Five PLLs (three global and two Serial RapidIO PLLs). • Two DDR controllers with up to a 400 MHz clock (800 MHz data rate), 64/32 bit data bus, supporting up to a total 2 Gbyte in up to four banks (two per controller) and support for DDR2 an |
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Freescale Semiconductor |
Tri-Core Digital Signal Processor em bus with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory o |
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Freescale Semiconductor |
Quad Digital Signal Processor data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peripherals, access by |
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Freescale Semiconductor |
Quad Core Digital Signal Processor m, core, global, and serial RapidIO). • DDR controller with up to a 200 MHz clock (400 MHz data rate), 16/32 bit data bus, supporting up to 1 Gbyte in up to two banks and support for DDR1 and DDR2. • DMA controller with 16 bidirectional channels with |
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Freescale Semiconductor |
Quad Core Digital Signal Processor dIO). • Security Engine (SEC0 optimized to process all the algorithms associated with IPSec, IKE, WTLS/WAP, SSL/TLS, and 3GPP using 4 crypto-channels with multi-command chains, integrated controller for assignment of the six execution units (PKEU, DE |
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Freescale Semiconductor |
Network Digital Signal Processor |
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Freescale Semiconductor |
Low-Cost 16-Bit DSP Features Table 1 lists the features of the Freescale MSC7110 device. Table 1. MSC7110 Features Feature Description • Up to 1000 MMACS using an internal 266 MHz clock at 1.2 V. A multiply-accumulate operation includes a multiply-add instruction with |
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Freescale Semiconductor |
Low-Cost 16-bit DSP for each buffer, and a write buffer. • System control unit performs software watchdog timer function; includes programmable bus time-out monitors on AHB-Lite slave buses; includes bus error detection and programmable time-out monitors on AHB-Lite mas |
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Freescale Semiconductor |
Low-Cost 16-bit DSP for each buffer, and a write buffer. • System control unit performs software watchdog timer function; includes programmable bus time-out monitors on AHB-Lite slave buses; includes bus error detection and programmable time-out monitors on AHB-Lite mas |
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Freescale Semiconductor |
Quad Digital Signal Processor with 64 or 32 bit data and 32-bit address bus, support for multi-master designs, four-beat burst transfers (eight-beat in 32-bit data mode), port size of 64/32/16/8 bits controlled by the internal memory controller,.access to external memory or peri |
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Freescale Semiconductor |
Quad-Core Digital Signal Processor d two differential). • Five PLLs (three global and two Serial RapidIO PLLs). • Multi-Accelerator Platform Engine for Baseband (MAPLE-B) with a programmable system interface, Turbo decoding, Viterbi decoding, and FFT/iFFT and DFT/iDFT processing. MAPL |
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Freescale Semiconductor |
Packet Telephony Farm Card User Guide of the MSC8102PFC are as follows (see Figure 2): • MSC8102PFC platform: — Digital support for up to 672 channels — PTMC Type 3 form card for interfacing to standard subsystems • MSC8101 aggregator — MSC8101 DSP communications processor with: — 10/100 |
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