| No. | Partie # | Fabricant | Description | Fiche Technique |
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ETCTI |
TCI6638K2K Multicore DSP+ARM KeyStone II System-on-Chip (SoC) (Rev. D) |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR • High-Performance Communications Infrastructure DSP (TCI6487/8) – 1-ns Instruction Cycle Time – 1.0-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – Commercial Temperature 0°C to 100°C • 3 TMS320C64x+™ DSP Cores – Dedicated SPLOOP Instructions – C |
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ETCTI |
TCI6630K2L Multicore DSP+ARM KeyStone II System-on-Chip (SoC) (Rev. E) |
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ETCTI |
TCI6636K2H Multicore DSP+ARM KeyStone II System-on-Chip (SoC) (Rev. F) |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible − Serial Peripheral Interface (SPI) Comp |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR 12 • Key Features – High-Performance Communications Infrastructure DSP (TCI6489) – 1.18-ns Instruction Cycle Time – 850-MHz Clock Rate – 0°C to 100°C Commercial Temperature – 3 TMS320C64x+™ DSP Cores; Six RSAs for CDMA Processing (2 per core) – One R |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR 1 • Six On-Chip TMS320C64x+ Megamodules • Endianess: Little Endian, Big Endian • C64x+ Megamodule Main Features: – High-Performance, Fixed-Point TMS320C64x+ DSP – 500/625/700 MHz – Eight 32-Bit Instructions/Cycle – 4000 MIPS/MMACS (16-Bits) at 500 MH |
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Texas Instruments |
Multicore Fixed and Floating-Point Digital Signal Processor om 1 2 3 4 5 6 7 8 9 10 11 List of Figures Lot Trace Code Example for TMS320TCI6602 (CYP Package) ...................................................... 5 Read DQS to DQ Eye Training - Board View ..................................................... |
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Texas Instruments |
Multicore Fixed and Floating-Point Digital Signal Processor om 1 2 3 4 5 6 7 8 9 10 11 List of Figures Lot Trace Code Example for TMS320TCI6604 (CYP Package) ...................................................... 5 Read DQS to DQ Eye Training - Board View ..................................................... |
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Texas Instruments |
Multicore Fixed and Floating-Point Digital Signal Processor om 1 2 3 4 5 6 7 8 9 10 11 List of Figures Lot Trace Code Example for TMS320TCI6608 (CYP Package) ...................................................... 5 Read DQS to DQ Eye Training - Board View ..................................................... |
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Texas Instruments |
Communications Infrastructure KeyStone SOC Can Cause Higher Than Expected Latency Usage Note (Page 97) SPRZ352D June 2013 • Added Advisory 31: Single MFENCE Issue (Page 55) • Added Advisory 32: Read Exception and Data Corruption Issue (Page 57) • Added Advisory 33: Incorrect Output from TAC |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR − Byte-Addressable (8-/16-/32-/64-Bit Data) − 8-Bit Overflow Protection − Bit-Field Extract, Set, Clear − Normalization, Saturation, Bit-Counting − Up to 256 Channels Each − ST-Bus-Switching-, AC97-Compatible − Serial Peripheral Interface (SPI) Comp |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR 12 • High-Performance Communications Infrastructure DSP (TCI6482) – 1.17-, 1-, and 0.83-ns Instruction Cycle Time – 850-MHz, 1-GHz, and 1.2-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – 9600 MIPS/MMACS (16-Bits) – Commercial Temperature [0°C to |
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Texas Instruments |
DIGITAL SIGNAL PROCESSOR • High-Performance Communications Infrastructure DSP (TCI6487/8) – 1-ns Instruction Cycle Time – 1.0-GHz Clock Rate – Eight 32-Bit Instructions/Cycle – Commercial Temperature 0°C to 100°C • 3 TMS320C64x+™ DSP Cores – Dedicated SPLOOP Instructions – C |
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Texas Instruments |
Communications Infrastructure KeyStone SOC 4 5 6 7 8 9 10 11 12 13 14 15 List of Figures Lot Trace Code Example for TMS320TCI6614 (CMS Package) ...................................................... 5 SRIO SerDes in Loopback Mode .............................................................. |
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Texas Instruments |
Communications Infrastructure KeyStone SOC Can Cause Higher Than Expected Latency Usage Note (Page 110) June 2013 • Added Advisory 39: Single MFENCE Issue (Page 63) • Added Advisory 40: Read Exception and Data Corruption Issue (Page 65) • Added Advisory 41: Incorrect Output from TAC for HS- |
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