| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Texas Instruments |
3-GHz 4-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator •1 3:1 Input Multiplexer – Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10-MHz to 40MHz Crystal or Single-Ended Clock • Two Banks With 2 Differential O |
|
|
|
|
Texas Instruments |
Ultra-Low Jitter LVCMOS Fanout Buffer and Level Translator •1 5 LVCMOS Outputs, DC to 200 MHz • Universal Input – LVPECL – LVDS – HCSL – SSTL – LVCMOS and LVTTL • Crystal Oscillator Interface – Crystal Input Frequency: 10 to 40 MHz • Output Skew: 6 ps • Additive Phase Jitter – 30 fs at 156.25 MHz (12 kHz to |
|
|
|
|
Texas Instruments |
Family Precision 0-Delay Clock Conditioner 12 • Integrated VCO with Very Low Phase Noise Floor • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz • VCO Divider Values of 2 to 8 (All Divides) – Bypassable with VCO Mux When Not in 0delay Mode • Channe |
|
|
|
|
Texas Instruments |
8-Output PCIe Gen1/Gen2/Gen3/Gen4/Gen5 Clock Buffer and Level Translator • 3:1 Input Multiplexer – Two Universal Inputs Operate up to 400 MHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10-MHz to 40-MHz Crystal or Single-Ended Clock • Two Banks With 4 Differential O |
|
|
|
|
Texas Instruments |
Ultra-Low Jitter Clock Generator •1 Ultra Low Noise, High Performance – Jitter: 100-fs RMS Typical, FOUT > 100 MHz – PSNR: –80 dBc, Robust Supply Noise Immunity • Flexible Device Options – Up to 8 AC-LVPECL, AC-LVDS, AC-CML, HCSL or LVCMOS Outputs, or Any Combination – Pin Mode, I2C |
|
|
|
|
Texas Instruments |
Four-Output Clock Buffer and Level Translator • 3:1 Input multiplexer – Two universal inputs operate up to 400 MHz and accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or single-ended clocks – One crystal input accepts a 10- to 40-MHz crystal or single-ended clock • Two banks with two differential ou |
|
|
|
|
Texas Instruments |
1.6GHz High Performance Clock Buffer Divider 1 •2 30 fs additive jitter (100 Hz to 20 MHz) • Dual clock inputs • Programmable output channels (0 to 1600 MHz) • External synchronization • Pin compatible family of clocking devices • 3.15 to 3.45 V operation • Package: 48 pin LLP (7.0 x 7.0 x 0.8 |
|
|
|
|
Texas Instruments |
Ultra-Low Jitter Network Synchronizer Clock •1 One Digital Phase-Locked Loop (DPLL) With: – Hitless Switching: ±50-ps Phase Transient – Programmable Loop Bandwidth With Fastlock – Standards-Compliant Synchronization and Holdover Using a Low-Cost TCXO/OCXO • Two Analog Phase-Locked Loops (APLLs |
|
|
|
|
Texas Instruments |
Low-Jitter Dual-Channel Network Synchronizer Clock •1 Two Independent PLL Channels Featuring: – Jitter: 150-fs RMS for Outputs ≥ 100 MHz – Phase Noise: –112 dBc/Hz at 100-Hz Offset for 122.88 MHz – Hitless Switching: 50-ps Phase Transient With Phase Cancellation – Programmable Loop Bandwidth With Fas |
|
|
|
|
Texas Instruments |
Low Additive Jitter LVDS Buffer • High-performance LVDS clock buffer family: up to 2 GHz – 2:12 differential buffer (LMK1D1212) – 2:16 differential buffer (LMK1D1216) • Supply voltage: 1.71 V to 3.465 V • Low additive jitter: < 60 fs RMS maximum in 12- kHz to 20-MHz at 156.25 MHz – |
|
|
|
|
Texas Instruments |
Clock Conditioner 12 • Integrated VCO with Very Low Phase Noise Floor • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz • VCO Divider Values of 2 to 8 (All Divides) • Channel Divider Values of 1, 2 to 510 (even divides) • L |
|
|
|
|
Texas Instruments |
Family Clock Jitter Cleaner 1 •23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO |
|
|
|
|
Texas Instruments |
Ultra Low-Noise JESD204B Compliant Clock Jitter Cleaner •1 JEDEC JESD204B Support • Ultra-Low RMS Jitter – 88 fs RMS Jitter (12 kHz to 20 MHz) – 91 fs RMS Jitter (100 Hz to 20 MHz) – –162.5 dBc/Hz Noise Floor at 245.76 MHz • Up to 14 Differential Device Clocks from PLL2 – Up to 7 SYSREF Clocks – Maximum C |
|
|
|
|
Texas Instruments |
Family Clock Jitter Cleaner 1 •23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Redundant Reference Inputs – Loss of Signal Detection – Automatic and Manual Selection of Reference Clock Input – PLL2 – Phase Detector Rate up to 100 MHz – Input Frequency-Doubler – Integrated VCO |
|
|
|
|
Texas Instruments |
Precision Clock Conditioner •1 20 fs Additive Jitter • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz • Clock Output Frequency Range of 1 to 800 MHz • 3 LVDS and 5 LVPECL Clock Outputs • Dedicated Divider and Delay Blocks on Each Cl |
|
|
|
|
Texas Instruments |
Family Low-Noise Clock Jitter Cleaner 1 •23 Cascaded PLLatinum™ PLL Architecture – PLL1 – Phase Detector Rate of up to 40 MHz – Integrated Low-Noise Crystal Oscillator Circuit – Dual Redundant Input Reference Clock with LOS – PLL2 – Normalized [1 Hz] PLL Noise Floor of 224 dBc/Hz – Phase |
|
|
|
|
Texas Instruments |
3-GHz 10-Output Ultra-Low Additive Jitter Differential Clock Buffer and Level Translator • 3:1 input multiplexer – Two universal inputs operate up to 3.1 ghz and accept lvpecl, lvds, cml, sstl, hstl, hcsl, or single-ended clocks – One crystal input accepts 10-mhz to 40-mhz crystal or single-ended clock • Two banks with five differential |
|
|
|
|
Texas Instruments |
3-GHz 6-Output Ultra-Low Additive Jitter Differential Clock Buffer/Level Translator •1 3:1 Input Multiplexer – Two Universal Inputs Operate up to 3.1 GHz and Accept LVPECL, LVDS, CML, SSTL, HSTL, HCSL, or Single-Ended Clocks – One Crystal Input Accepts a 10 to 40 MHz Crystal or Single-Ended Clock • Two Banks with 3 Differential Outp |
|
|
|
|
Texas Instruments |
High-Performance Ultra-Low Jitter Oscillator •1 Ultra-low Noise, High Performance – Jitter: 90 fs RMS Typical Fout > 100 MHz – PSRR: –70 dBc, Robust Supply Noise Immunity • Supported Output Format – LVPECL up to 1 GHz – LVDS up to 900 MHz – HCSL up to 400 MHz • Total Frequency Tolerance of ± 50 |
|
|
|
|
Texas Instruments |
Clock Conditioner 12 • Integrated VCO with Very Low Phase Noise Floor • Integrated Integer-N PLL with Outstanding Normalized Phase Noise Contribution of -224 dBc/Hz • VCO Divider Values of 2 to 8 (All Divides) • Channel Divider Values of 1, 2 to 510 (even divides) • L |
|