| No. | Partie # | Fabricant | Description | Fiche Technique |
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Texas Instruments |
Enhanced CMOS Quad Differential Line Driver 1 • Meets TIA/EIA-422-B (RS-422) and ITU-T V.11 Recommendation • Interoperable With Existing 5V RS-422 Networks • Ensured VOD of 2V Min Over Operating Conditions • Balanced Output Crossover for Low EMI (Typical Within 40 mV of 50% Voltage Level) • Lo |
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Texas Instruments |
FPGA-Link Deserializer 1 •2 5-bit DDR LVDS Parallel Data Interface • Programmable Receive Equalization • Selectable DC-Balance Decoder • Selectable De-Scrambler • Remote Sense for Automatic Detection and Negotiation of Link Status • No External Receiver Reference Clock Req |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL RECEIVERS • Meets or Exceeds the Requirements of ANSI EIA/TIA-644 Standard for Signaling Rates (1) up to 400 Mbps • Operates With a Single 3.3-V Supply • –2-V to 4.4-V Common-Mode Input Voltage Range • Differential Input Thresholds <50 mV With 50 mV of Hystere |
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ETCTI |
3-to1 DVI/DMI Switch (Rev. B) |
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Texas Instruments |
FPGA-Link Deserializer 1 •2 5-bit DDR LVDS Parallel Data Interface • Programmable Receive Equalization • Selectable DC-Balance Decoder • Selectable De-Scrambler • Remote Sense for Automatic Detection and Negotiation of Link Status • No External Receiver Reference Clock Req |
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Texas Instruments |
HIGH-SPEED DIFFERENTIAL RECEIVERS that implement the electrical characteristics of low-voltage differential signaling (LVDS). LVDS is defined in the TIA/EIA-644 standard. This improved performance represents the second generation of receiver products for this standard providing a bet |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Four- ('390), Eight- ('388A), or Sixteen- ('386) Line Receivers Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Integrated 110-Ω Line Termination Resistors on LVDT Products • Designed for Signaling Rates Up to 250 Mbps • SN65 Versio |
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Texas Instruments |
High-Speed Differential Line Drivers •1 Four ('391), Eight ('389), or Sixteen ('387) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard • Designed for Signaling Rates Up to 630 Mbps With Very Low Radiation (EMI) • Low-Voltage Differential Signaling With Typical Ou |
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Texas Instruments |
High-Speed Differential Line Drivers •1 Four ('391), Eight ('389), or Sixteen ('387) Line Drivers Meet or Exceed the Requirements of ANSI EIA/TIA-644 Standard • Designed for Signaling Rates Up to 630 Mbps With Very Low Radiation (EMI) • Low-Voltage Differential Signaling With Typical Ou |
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Texas Instruments |
Programmable 27-Bit Parallel-to-Serial Transmitter • FlatLink™3G serial interface technology • Compatible with FlatLink3G receivers such as SN65LVDS302 • Input supports 24-bit RGB video mode interface • 24-Bit RGB data, 3 control bits, 1 parity bit and 2 reserved bits transmitted over 1, 2 or 3 diffe |
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Texas Instruments |
PROGRAMMABLE 27-BIT DISPLAY SERIAL INTERFACE TRANSMITTER • FlatLink™3G Serial-Interface Technology • Compatible With FlatLink3G Receivers Such as SN65LVDS306 • Input Supports 24-bit RGB Video Mode Interface • 24-Bit RGB Data, 3 Control Bits, 1 Parity Bit, and 2 Reserved Bits Transmitted Over One Differenti |
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Texas Instruments |
Quad Differential Bus Transceiver 1 •2 Pinout for IPI Interface • Compact 20-pin PLCC Package • Meets EIA-485 Standard for Multipoint Bus Transmission • Greater than 60 mA Source/Sink • Thermal Shutdown Protection DESCRIPTION The DS36950 is a low power, space-saving quad EIA-485 dif |
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Texas Instruments |
FPGA-Link Serializer 1 •2 5-bit DDR LVDS Parallel Data Interface • Programmable Transmit De-emphasis • Configurable Output Levels (VOD) • Selectable DC-balanced Encoder • Selectable Data Scrambler • Remote Sense for Automatic Detection and Negotiation of Link Status • On |
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Texas Instruments |
Multipoint RS485/RS422 Transceivers 1 •2 Meets EIA Standard RS485 for Multipoint Bus Transmission and is Compatible with RS-422 • 10 Ns Driver Propagation Delays (Typical) • Single +5V Supply • −7V to +12V Bus Common Mode Range Permits ±7V Ground Difference between Devices on the Bus • |
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Texas Instruments |
Quad Differential Bus Transceiver 1 •2 Pinout for SCSI Interface • Compact 20-Pin PLCC or SOIC Package • Meets EIA-485 Standard for Multipoint Bus Transmission • Greater than 60 mA Source/Sink Currents • Thermal Shutdown Protection • Glitch-Free Driver Outputs on Power Up and Down D |
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Texas Instruments |
High-Speed Differential Line Receivers •1 Meet or Exceed the Requirements of ANSI TIA/EIA-644 Standard • Operate With a Single 3.3-V Supply • Designed for Signaling Rates of up to 150 Mbps (See ) • Differential Input Thresholds ±100 mV Max • Typical Propagation Delay Time of 2.1 ns • Powe |
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