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3 Amp. Glass Passivated Ultrafast Recovery Rectifier Characteristics at Tamb = 25 °C VF IR Rthj-a Max. forward voltage drop at IF = 3 A Max. reverse current at VRRM at 25 ºC 0.98 V 10 µA 30 °C/W 1.25 V Max. thermal resistance ( l = 10 mm.) Jul - 03 31DF2.....31DF4 Rating And Characteristic Curves F |
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3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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MINIATURE GLASS PASSIVATED JUNCTION PLASTIC RECTIFIER |
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500mW UNIBLOC SILICON OXIDE-PASSIVATED ZENER REGULATOR DIODES itive with respect to anode.) MOUNTING POSITION, Any WEIGHT, 0.18 gram lapprox) FIGURE 1 - POWER- DERATING J 800 ~""8" "- 3' .§ , , - V ~ z '>'K. :;0:: 600 ill 0 L"318" L" 114" "- """ ~"" ~'" 400 . """~"'" ''x"" 200 .. '" '~" o " o 20 |
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FOUR POLE LOW PASS VCF |
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3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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Micro.compass • • • • • • • • Accelerometer and magnetometer board for the Sensinode Micro Series 3-axis 2.5G - 10 G accelerometers (selectable range) 3-axis magnetometers Uses a Cypress PSoC microcontroller for on-board processing Can be configured as a digital |
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Low Pass Filter • High rejection, 36 dB typical • Sharp insertion loss roll-off • Miniature shielded case • Aqueous washable Applications • Defence communications • Transmitters / receivers • Harmonic rejection Electrical Specifications at 25°C Parameter F# Pass |
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CIF COLOR CMOS IMAGE SENSOR |
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GLASS PASSIVATED JUNCTION TRANSIENT VOLTAGE SUPPRESSOR STANDOFF VOLTAGE- 5.0 to 45.0V 1500 Watt Peak Power • Plastic package has Underwriters Laboratory Flammability Classification 94 V-O • Glass passivated chip junction in Molded Plastic package • 1500W surge capability at 1ms • Excellent clamping capability • Low zener inpedance • Fast response time: ty |
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