| No. | Partie # | Fabricant | Description | Fiche Technique |
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ETC |
Vertical Deflection s Power Amplifier s Flyback Generator s Thermal Protection DESCRIPTION The TDA8172 is a monolithic integrated circuit in HeptawattTM package. It is a high efficiency power booster for direct driving of vertical windings of TV yokes. It is intended fo |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator • Member of programmable clock generator family – CDCE913/CDCEL913: 1-PLL, 3 outputs – CDCE925/CDCEL925: 2-PLL, 5 outputs – CDCE937/CDCEL937: 3-PLL, 7 outputs – CDCE949/CDCEL949: 4-PLL, 9 outputs • In-system programmability and EEPROM – Serial progra |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator • Member of programmable clock generator family – CDCE913/CDCEL913: 1-PLL, 3 outputs – CDCE925/CDCEL925: 2-PLL, 5 outputs – CDCE937/CDCEL937: 3-PLL, 7 outputs – CDCE949/CDCEL949: 4-PLL, 9 outputs • In-system programmability and EEPROM – Serial progra |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator •1 Member of Programmable Clock Generator Family – CDCEx913: 1 PLLs, 3 Outputs – CDCEx925: 2 PLLs, 5 Outputs – CDCEx937: 3 PLLs, 7 Outputs – CDCEx949: 4 PLLs, 9 Outputs • In-System Programmability and EEPROM – Serial Programmable Volatile Register – |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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ETC |
Photomicrosensor (Reflective) • The LED requires a forward current of only 5 mA due to the PhotoDarlington transistor built into the detector. • With a red LED light source. ■ Absolute Maximum Ratings (Ta = 25°C) Four, 0.125 Item Emitter Forward current Pulse forward current Re |
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Texas Instruments |
Automotive Control Area Network Flexible Data-Rate Controller •1 AEC Q100: qualified for automotive applications – Temperature grade 1: –40°C to 125°C TA • CAN FD controller with integrated CAN FD transceiver and serial peripheral interface (SPI) • CAN FD controller supports both ISO 118981:2015 and Bosch M_CAN |
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Texas Instruments |
Flexible Low Power LVCMOS Clock Generator •1 Member of Programmable Clock Generator Family – CDCEx913: 1-PLL, 3 Outputs – CDCEx925: 2-PLL, 5 Outputs – CDCEx925: 3-PLL, 7 Outputs – CDCEx949: 4-PLL, 9 Outputs • In-System Programmability and EEPROM – Serial Programmable Volatile Register – Nonv |
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ETC |
3.3V and 5.0V pASIC 2 FPGA Combining Speed/ Density/ Low Cost and Flexibility -3.3V and 5.0V operation with low standby power -I/O pin-compatibility between different devices in the same packages -PCI compliant (at 5.0V), full speed 33 MHz implementations -High design security provided by security fuses QL2009 Block Diagram 6 |
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