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ETC |
Safety Standard Capacitor Small Size with good self-healing effect. Have strong moisture resistance and well proof voltage. s Security Certifications Authentication Mark Profile No. E246678 UL1414 E314875 UL1283 40008924 CQC06001018191 SU03022-6001A SU03002-6002A SU03022-6003 |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETCTI |
MF10 Universal Monolithic Dual Switched Capacitor Filter (Rev. C) |
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Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE 1Y 11 3C 10 3B 9 3A 8 3Y SN54F10 . . . FK PACKAGE (TOP VIEW) 1C VCC NC 1A 1B 2A 3 2 1 20 19 4 18 1Y NC 5 17 NC 2B 6 16 3C NC 7 15 NC 2C 8 14 3B 9 10 11 12 13 3A 3Y NC GND 2Y NC – No internal connection logic diagram, each ga |
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Texas Instruments |
TRIPLE 3-INPUT POSITIVE-NAND GATE 1Y 11 3C 10 3B 9 3A 8 3Y SN54F10 . . . FK PACKAGE (TOP VIEW) 1C VCC NC 1A 1B 2A 3 2 1 20 19 4 18 1Y NC 5 17 NC 2B 6 16 3C NC 7 15 NC 2C 8 14 3B 9 10 11 12 13 3A 3Y NC GND 2Y NC – No internal connection logic diagram, each ga |
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Texas Instruments |
DUAL J-K POSITIVE-EDGE-TRIGGERED FLIP-FLOP D-type flip-flops if J and K are tied together. The SN54F109 is characterized for operation over the full military temperature range of – 55°C to 125°C. The SN74F109 is characterized for operation from 0°C to 70°C. SN54F109 . . . J PACKAGE SN74F109 |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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