No. | Partie # | Fabricant | Description | Fiche Technique |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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ETC |
16/000 Usable PLD Gate QuickRAM ESP Combining Performance/ Density and Embedded RAM up to 16 simultaneous inputs and five outputs within a cell that can be fragmented into five independent cells. Each cell has a fanin of 29 including register and control lines (see Figure 3). WDATA RAM Module (1,152 bits) RDATA WADDR RADDR RAM |
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