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ETC |
4-BIT BINARY FULL ADDER W/FAST CARRY |
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ETC |
8-Bit Microcontroller CPU configuration z 2K*14 bits on-chip ROM z 80*8 bits on-chip registers (SRAM) z 8-level stacks for subroutine nesting z Less than 1.9 mA at 5V/4MHz z Typically 15uA, at 3V/32kHz z Typically 1 uA, during Sleep mode I/O port configuration z 3 bidirec |
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Texas Instruments |
4-Bit DRAM ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 2003 Powered by ICminer.com Electronic-Library Service CopyRight 20 |
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Texas Instruments |
4-BIT SYNCHRONOUS UP/DOWN COUNTERS allows the counters to be used as modulo-N dividers simply by modifying the count length with the preset inputs. A clear (CLR) input has been provided that forces all outputs to the low level when a high level is applied. The clear function is indepe |
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Texas Instruments |
8-Bit Shift Registers • 8-bit serial-in, parallel-out shift • Wide operating voltage range of 2 V to 6 V • High-current 3-state outputs can drive up to 15 LSTTL loads • Low power consumption: 80-μA (maximum) ICC • tpd = 13 ns (typical) • ±6-mA output drive at 5 V • Low in |
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Texas Instruments |
Low Power 12-Bit DAC • 12-Bit Voltage Output DAC • Programmable Internal Reference • Programmable Settling Time: – 1 µs in Fast Mode – 3.5 µs in Slow Mode • Compatible With TMS320 and SPI™ Serial Ports • Differential Nonlinearity . . . <0.5 LSB Typ • Monotonic Over Tempe |
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Texas Instruments |
16- and 32-Bit RISC Flash Microcontroller 1 • High-Performance Automotive-Grade Microcontroller for Safety-Critical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Vo |
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Texas Instruments |
16- and 32-Bit RISC Flash Microcontroller 1 • High-Performance Microcontroller for SafetyCritical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test for CPU and On-Chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Monitorin |
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ETC |
general purpose 32-bit microprocessors his datasheet, or any error or omission in such information, or any incorrect use of the product. Change Log Issue A (Draft 0.1) (Draft 0.2) B C D draft1 D E Date Sept 1994 Oct 1994 Dec 1994 Dec 1994 Mar 1995 Mar 1995 Mar 1995 Aug 1995 By EH/BJH EH |
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Texas Instruments |
16- and 32-Bit RISC Flash Microcontroller 1 • High-Performance Microcontroller for SafetyCritical Applications – Dual CPUs Running in Lockstep – ECC on Flash and RAM Interfaces – Built-In Self-Test (BIST) for CPU and On-chip RAMs – Error Signaling Module With Error Pin – Voltage and Clock Mo |
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Texas Instruments |
8-Bit Parallel-Out Serial Shift Registers •1 Wide Operating Voltage Range of 2 V to 6 V • Outputs Can Drive Up to 10 LSTTL Loads • Low Power Consumption, 80-μA Maximum ICC • Typical tpd = 20 ns • ±4-mA Output Drive at 5 V • Low Input Current of 1-μA Maximum • AND-Gated (Enable/Disable) Seria |
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ETC |
8-Bit Microcontroller z ROM size: 2K x 16 bits z Interrupt events: z RAM: 51 x 8 bits(Special Purpose Register) (a) External interrupt (PA7~PA0). + 128 x 8 (General Purpose Register) (b) Internal timer/event counter interrupt z STACK: 8 Levels (TM0~TM4, PWM1, PWM2) |
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ETC |
ADC-8051 10-bit microcontrollers 3/VLPD/AN3/TMS 10 P1.2/INT2/AN2/TDO 9 P3.7/T1/PWM 4.2 ZEN3305A/09A-DIP/SOP 20Pin, ZEN3308A-TSSOP 20Pin RESET/P4.0 RXD/P3.0 TXD/P3.1 XTAL2/P4.1 XTAL1/P4.2 INT0/P3 2 INT1/P3 3 T0/P3.4 PWM/T1/P3.5 GND 1 2 3 4 5 6 7 8 9 10 20 19 18 17 16 15 14 13 12 |
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Texas Instruments |
4-Bit Parallel Access Register Description • Asynchronous Master Reset • J, K, (D) Inputs to First Stage • Fully Synchronous Serial or Parallel Data Transfer • Shift Right and Parallel Load Capability • Complementary Output From Last Stage • Buffered Inputs • CTyLp=ic1a5l pfMF,A |
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Texas Instruments |
18-Bit Analog-to-Digital Converter (ADC) Drivers •1 Excellent Dynamic Performance: – Low Distortion: –122 dBc for HD2 and –140 dBc for HD3 at 100 kHz – Gain Bandwidth (G = 100): 120 MHz – Slew Rate: 115 V/µs – 16-Bit Settling at 4-V Step: 280 ns – Low Voltage Noise: 2.5 nV/√Hz at 10 kHz – Low Outpu |
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Texas Instruments |
8-Bit Binary Counter ual positive-edge triggered clocks. The function tables show the operation of the counter clock-enable (CCKEN, CCKEN) and output-enable (OE, OE) inputs. The counter input has direct load and clear functions. A low-going RCO pulse is obtained when the |
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Texas Instruments |
16-Bit Buffer/Drivers or one 16-bit buffer. These devices provide true outputs and complementary output-enable (OE and OE) inputs. 54ACT16241 . . . WD PACKAGE 74ACT16241 . . . DL PACKAGE (TOP VIEW) 1OE 1Y1 1Y2 GND 1Y3 1Y4 VCC 2Y1 2Y2 GND 2Y3 2Y4 3Y1 3Y2 GND 3Y3 3Y4 VCC |
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Texas Instruments |
16-BIT REGISTERED TRANSCEIVERS t control in either direction of data flow. The A-to-B enable (CEAB) input must be low to enter data from A or to output data to B. If both CEAB and CLKAB are low, then B port will have the level of A port prior to the most recent low-to-high transit |
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Texas Instruments |
Presettable Synchronous 4-Bit Up/Down Counters • Synchronous Counting and Asynchronous Loading • Two Outputs for N-Bit Cascading • Look-Ahead Carry for High-Speed Counting • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . |
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Texas Instruments |
8-Bit Parallel-In/Serial-Out Shift Register Description • Buffered Inputs • Asynchronous Parallel Load • Complementary Outputs • Fanout (Over Temperature Range) - Standard Outputs . . . . . . . . . . . . . . . 10 LSTTL Loads - Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads • Wid |
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