| No. | Partie # | Fabricant | Description | Fiche Technique |
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Cypress Semiconductor |
USB Type-C Port Controller |
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Cypress Semiconductor |
Low-Voltage 64/256/512/1K/2K/4K/8K x 9 Synchronous FIFOs • High-speed, low-power, first-in, first-out (FIFO) memories • 64 x 9 (CY7C4421V) • 256 x 9 (CY7C4201V) • 512 x 9 (CY7C4211V) • 1K x 9 (CY7C4221V) • 2K x 9 (CY7C4231V) • 4K x 9 (CY7C4241V) • 8K x 9 (CY7C4251V) • High-speed 66-MHz operation (15-ns rea |
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Cypress Semiconductor |
PSoC-62 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress Semiconductor |
2 Gbit (256 Mbyte) 3.0V Flash Memory a Write Buffer that allows a maximum of 256 words/512 bytes to be programmed in one operation, resulting in faster effective programming time than standard single byte/word programming algorithms. This makes the device an ideal product for today’s em |
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Cypress Semiconductor |
32K/64Kx18 Deep Sync FIFOs • High-speed, low-power, first-in first-out (FIFO) memories • 32K x 18 (CY7C4275) • 64K x 18 (CY7C4285) • 0.5 micron CMOS for optimum speed/power • High-speed 100-MHz operation (10-ns read/write cycle times) • Low power — ICC=50 mA • • • • • • • • • |
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Cypress Semiconductor |
Dual Programmable Clock Generator • Two independent clock outputs ranging from 320 kHz to 100 MHz • Individually programmable PLLs use 22-bit serial word • Low-skew ÷1,÷2, and ÷4 CLKA outputs • Phase-locked loop oscillator input derived from external low-frequency reference clock (1 |
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Cypress Semiconductor |
4-Mbit (256K words x 16 bit) Static RAM ■ High speed: 45 ns/55 ns ■ Ultra-low standby power ❐ Typical standby current: 3.5 A ❐ Maximum standby current: 8.7 A ■ Embedded ECC for single-bit error correction[1, 2] ■ Wide voltage range: 1.65 V to 2.2 V, 2.2 V to 3.6 V, and 4.5 V to 5.5 V ■ 1 |
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Cypress Semiconductor |
Simultaneous Read/Write Flash Supports Common Flash Memory Interface (CFI) Erase suspend/erase resume – Suspends erase operations to read data from, or program data to, a sector that is not being erased, then resumes the erase operation Data# polling and toggle bits – Provi |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated |
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Cypress Semiconductor |
Embedded Bluetooth-4.2 SoC |
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Cypress Semiconductor |
Microcontroller 32-bit ARM Cortex-M0+ Core Processor version: r0p1 Maximum operating frequency: 40.8 MHz Nested Vectored Interrupt Controller (NVIC): 1 NMI (non-maskable interrupt) and 24 peripheral interrupt with 4 selectable interrupt priority levels 24-bit Sy |
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Cypress Semiconductor |
Microcontroller 32-bit ARM Cortex-M4F Core Processor version: r0p1 Up to 160 MHz frequency operation Built-in FPU Supports DSP instructions Memory Protection Unit (MPU): improves the reliability of an embedded system Integrated Nested Vectored Interrupt Contr |
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Cypress Semiconductor |
Dual Serial Input PLL • Operating voltage: 2.7 V to 5.5 V • PLL1 operating frequency: — 2.5 GHz with prescaler ratios of 32/33 and 64/65 • PLL2 operating frequency: — 600 MHz with prescaler ratios of 8/9 and 16/17 • Lock detect feature • Available in a 20-pin TSSOP (Thin |
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Cypress Semiconductor |
256K (32K x 8) Static RAM ■ Temperature range ❐ –40 °C to 85 °C ■ Pin and function compatible with CY7C199C ■ High speed ❐ tAA = 10 ns ■ Low active power ❐ ICC = 80 mA at 10 ns ■ Low CMOS standby power ❐ ISB2 = 3 mA ■ 2.0 V data retention ■ Automatic power-down when deselecte |
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Cypress Semiconductor |
High-Performance LVDS Oscillator ■ Low-jitter crystal oscillator (XO) ■ Less than 1 ps typical root mean square (RMS) phase jitter ■ Low-voltage differential signaling (LVDS) output ■ Output frequency from 50 MHz to 690 MHz ■ Factory-configured or field-programmable ■ Integrated pha |
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Cypress Semiconductor |
Single-Chip Bluetooth Transceiver Bluetooth Subsystem ■ Complies with Bluetooth core specification version 5.0 with LE 2-Mbps support ■ Supports Basic Rate (BR) and Bluetooth Low Energy (BLE) ■ Supports Adaptive Frequency Hopping (AFH) ■ Programmable TX power up to 12 dBm ■ Rx sensit |
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Cypress Semiconductor |
5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated |
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Cypress Semiconductor |
1-Mbit nvSRAM ■ 1-Mbit nonvolatile static random access memory (nvSRAM) ❐ 25 ns and 45 ns access times ❐ Internally organized as 128K × 8 (CY14B101KA) or 64K × 16 (CY14B101MA) ❐ Hands off automatic STORE on power-down with only a small capacitor ❐ STORE to Quantum |
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Cypress Semiconductor |
Boot Sector Flash ❐ A hardware method of locking a sector to prevent any program or erase operations within that sector ❐ Sectors can be locked in-system or via programming equipment ❐ Temporary Sector Unprotect feature allows code changes in previously locked sectors |
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Cypress Semiconductor |
Frequency Generator for Integrated Core Logic • Maximized EMI suppression using Cypress’s Spread Spectrum Technology • Low jitter and tightly controlled clock skew • Highly integrated device providing clocks required for CPU, core logic, and SDRAM • Two copies of CPU clocks • Nine copies of SDRA |
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