Cypress Semiconductor CY3 fiche technique

No.	Partie #	Fabricant	Description
1	CY37064VP100-100BBC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
2	CY37512VP208-66NC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
3	CY37064P44-154AI	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
4	CY37128P84-125JC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
5	CY37256VP256-66BGI	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
6	CY37384P256-83BGC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
7	CY37512P208-83NC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
8	CY37032	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
9	CY37128P84-167JC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
10	CY37032VP48-100BAC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
11	CY37064P100-125AC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
12	CY37192P160-83AC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
13	CY3681	Cypress Semiconductor	EZ-USB FX2 USB Microcontroller High-speed USB Peripheral Controller ............................................................................................................. 6 2.0 APPLICATIONS .........................................................................................................................
14	CY37032P44-125AC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
15	CY37032P44-125JC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
16	CY37032VP44-143AC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
17	CY37032VP48-100BAI	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
18	CY37064VP44-100AI	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
19	CY37064VP48-100BAC	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated
20	CY37128	Cypress Semiconductor	5V/ 3.3V/ ISR High-Performance CPLDs • In-System Reprogrammable™ (ISR™) CMOS CPLDs — JTAG interface for reconfigurability — Design changes do not cause pinout changes — Design changes do not cause timing changes • High density — 32 to 512 macrocells — 32 to 264 I/O pins — Five dedicated