| No. | Partie # | Fabricant | Description | Fiche Technique |
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Cypress Semiconductor |
PSoC-62 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress |
PSoC-62 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm6® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress Semiconductor |
Powerline Communication ■ Integrated Powerline Modem PHY ■ 2400 bps Frequency Shift Keying Modulation ■ Powerline Optimized Network Protocol ■ Integrates Data Link, Transport, and Network Layers ■ Supports Bidirectional Half-Duplex Communication ■ 8-bit CRC Error Detection |
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Cypress Semiconductor |
PSoC-62 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress |
PSoC-61 MCU Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) with single-cycle multiply (Floating Point and Memory Protection Unit) ■ 100-MHz Cort |
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Cypress Semiconductor |
Configurable IOs ■ Overview The CapSense ExpressTM controller allows the control of 8 IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up t |
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Cypress Semiconductor |
Programmable System-on-Chip 32-bit MCU Sub-system ■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 32 kB of flash with Read Accelerator ■ Up to 4 kB of SRAM Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive a |
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Cypress |
PSoC-63 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress |
32-bit MCU 32-bit MCU Subsystem ■ 48-MHz ARM Cortex-M0+ CPU ■ Up to 64 KB of flash with Read Accelerator ■ Up to 8 KB of SRAM Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive and Comparator modes and ADC |
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Cypress Semiconductor |
PSoC Programmable System-on-Chip ■ Powerful Harvard-architecture processor ❐ M8C processor speeds up to 24 MHz ❐ 8 × 8 multiply, 32-bit accumulate ❐ Low power at high speed ❐ Operating voltage: 3.0 V to 5.25 V ❐ Operating voltages down to 1.0 V using on-chip switch mode pump (SMP) ❐ |
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Cypress Semiconductor |
Configurable IOs ■ Overview The CapSense ExpressTM controller allows the control of 6 IOs configurable as capacitive sensing buttons or as GPIOs for driving LEDs or interrupt signals based on various button conditions. The GPIOs are also configurable for waking up t |
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Cypress Semiconductor |
PSoC Programmable System-on-Chip ■ Low power CapSense® block ❐ Configurable capacitive sensing elements ❐ Supports combination of CapSense buttons, sliders, touchpads, and proximity sensors ■ Powerful Harvard-architecture processor ❐ M8C processor speeds running up to 12 MHz ❐ Low p |
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Cypress Semiconductor |
CapSense Applications ■ Low Power CapSenseTM Block ❐ Configurable Capacitive Sensing Elements ❐ Supports Combination of CapSense Buttons, Sliders, Touchpads, TouchScreens, and Proximity Sensors Powerful Harvard Architecture Processor ❐ M8C Processor Speeds Running to 24 |
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Cypress Semiconductor |
Proximity Sensors an advanced analog sensing channel and the Capacitive Sigma Delta PLUS (CSD PLUS) sensing algorithm, which delivers a signal-to-noise ratio (SNR) of greater than 100:1 to ensure touch accuracy even in extremely noisy environments. These controllers a |
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Cypress Semiconductor |
Programmable System-on-Chip 32-bit MCU Sub-system ■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 32 kB of flash with Read Accelerator ■ Up to 4 kB of SRAM Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive a |
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Cypress Semiconductor |
Programmable System-on-Chip 32-bit MCU Sub-system ■ 24-MHz ARM Cortex-M0 CPU with single-cycle multiply ■ Up to 32 kB of flash with Read Accelerator ■ Up to 4 kB of SRAM Programmable Analog ■ Two opamps with reconfigurable high-drive external and high-bandwidth internal drive a |
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Cypress |
PSoC-62 MCU 32-bit Dual CPU Subsystem ■ 150-MHz Arm6® Cortex®-M4F (CM4) CPU with single-cycle multiply, floating point, and memory protection unit (MPU) ■ 100-MHz Cortex-M0+ (CM0+) CPU with single-cycle multiply and MPU ■ User-selectable core logic operation at |
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Cypress |
Programmable System-on-Chip Operating characteristics Voltage range: 1.71 to 5.5 V, up to 6 power domains Temperature range (ambient) –40 to 85 °C[1] DC to 80-MHz operation Power modes • Active mode 3.1 mA at 6 MHz, and 15.4 mA at 48 MHz • 2-µA sleep mode • 300-nA hi |
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Cypress |
PSoC-61 MCU Note: In PSoC 61 the Cortex M0+ is reserved for system functions, and is not available for applications. 32-bit Dual CPU Subsystem ■ 150-MHz Arm® Cortex®-M4F (CM4) with single-cycle multiply (Floating Point and Memory Protection Unit) ■ 100-MHz Cort |
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Cypress Semiconductor |
1.8V CapSense Controller ■ QuietZone™ Controller ❐ Patented Capacitive Sigma Delta PLUS (CSD PLUS™) sensing algorithm for robust performance ❐ High Sensitivity (0.1 pF) and best-in-class SNR performance to support: • Overlay thickness of 15 mm for glass and 5 mm plastic • Pr |
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