| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
|
|
|
Cirrus Logic |
Fractional-N Clock Synthesizer & Clock Multiplier Delta-Sigma Fractional-N Frequency Synthesis – Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Multiplier • I²C/SPI control port • Fractional clock multiplier and jitter reduction using hybrid analog/digital PLL — Generates low-jitter 6 –75 MHz clock (CLK_OUT), synchronized to a 50 Hz –30 MHz low-quality or intermittent frequency reference (CLK_IN) • Fle |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Synthesizer and Multiplier • I²C/SPI control port • Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL — Generates low-jitter 6 –75 MHz clock (CLK_OUT) from 8 –75 MHz timing reference (REF_CLK_IN) • Fractional clock multiplier and jitter reduction us |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Synthesizer & Clock Multiplier Delta-Sigma Fractional-N Frequency Synthesis – Generates a Low Jitter 6 - 75 MHz Clock from an 8 - 75 MHz Reference Clock Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 50 Hz to 30 MHz Clock Source |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Multiplier Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 50 Hz to 30 MHz Clock Source Internal LCO Reference Clock Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in HighResolution M |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Synthesizer and Clock Multiplier • Clock frequency synthesizer incorporating delta-sigma fractional-N analog PLL — Generates low-jitter 6 –75 MHz clock (CLK_OUT) from 8 –75 MHz timing reference (REF_CLK_IN) • Fractional clock multiplier and jitter reduction using hybrid analog/digital |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Multiplier Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Internal LC Oscillator for Timing Reference Highly Accurate PLL Multiplication Factor – Maximum Error less |
|
|
|
|
Cirrus Logic |
Clock Multiplier Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 23 kHz to 30 MHz Clock Source Internal LCO Reference Clock 128 Hz Loop Filter Bandwidth Selectable Multiplication Factors – 1x, 4x, 128x, and 256x |
|
|
|
|
Cirrus Logic |
Clock Multiplier Clock Multiplier / Jitter Reduction – Generates a Low Jitter 6 - 75 MHz Clock from a Jittery 750 kHz to 30 MHz Clock Source Internal LCO Reference Clock 1 Hz Loop Filter Bandwidth Selectable Multiplication Factors – 1x, 2x, 4x, and 8x Outpu |
|
|
|
|
Cirrus Logic |
WIRELESS PCI/USB CONTROLLER |
|
|
|
|
Cirrus Logic |
WIRELESS PCI/USB CONTROLLER |
|
|
|
|
Cirrus Logic |
WIRELESS 10BT CONTROLLER |
|
|
|
|
Cirrus Logic |
Fractional-N Clock Multiplier Clock Multiplier / Jitter Reduction Generates a Low Jitter 6 - 75 MHz Clock from a Jittery or Intermittent 50 Hz to 30 MHz Clock Source Highly Accurate PLL Multiplication Factor – Maximum Error Less Than 1 PPM in HighResolution Mode ® |
|
|
|
|
Cirrus Logic |
WIRELESS PCI/USB CONTROLLER |
|