| No. | Partie # | Fabricant | Description | Fiche Technique |
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Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
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Altera Corporation |
Programmable Logic Device .. f ■ High-performance 3.3-V EEPROM-based programmable logic devices (PLDs) built on second-generation Multiple Array MatriX (MAX®) architecture (see Table 1) ■ 3.3-V in-system programmability (ISP) through the built-in IEEE Std. 1149.1 Joint Test |
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Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
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|
Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
|
|
|
|
Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
|
|
|
|
Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
|
|
|
|
Altera Corporation |
Max 9000(a) Programmable Logic Device Family (6k Gates) .. ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ ■ High-performance CMOS EEPROM-based programmable logic devices (PLDs) built on third-generation Multiple Array MatriX (MAX®) architecture 5.0-V in-system programmability (ISP) through built-in IEEE Std. 1149.1 Joint Tes |
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