Aeroflex Circuit Technology UT fiche technique

No.	Partie #	Fabricant	Description
1	UT54ACS157	Aeroflex Circuit Technology	Quadruple 2 to 1 Multiplexers 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack UT54ACS157 - SMD 5962-96552 UT54ACTS157 - SMD 5962-96553 DESCRIPTION Th
2	UT54ACS164646S	Aeroflex Circuit Technology	Schmitt CMOS 16-bit Bidirectional MultiPurpose Registered Transceiver  Flexible voltage operation - 5V bus to 3.3V bus - 3.3V bus to 5V bus - 5V bus to 5V bus - 3.3V bus to 3.3V bus  Independent registers for A and B buses  Multiplexed real-time and stored data  Flow-through architecture optimizes PCB layout  Cold
3	7005	Aeroflex Circuit Technology	ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ Subsystem • Incorporates Transceivers, Protocol, and System Interface Components into a Single Hybrid Package • Functions as a Remote Terminal or Bus Controller • Interfaces to µP as a Simple Peripheral Unit CIRCUIT TECHNOLOGY www.aeroflex.com • +5V Operation
4	UT28F256	Aeroflex Circuit Technology	Radiation-Hardened 32K x 8 PROM q Programmable, read-only, asynchronous, radiationhardened, 32K x 8 memory - Supported by industry standard programmer q 45ns and 40ns maximum address access time (-55 oC to +125 oC) q TTL compatible input and TTL/CMOS compatible output levels q Thre
5	UT28F256LV	Aeroflex Circuit Technology	Radiation-Hardened 32K x 8 PROM q Programmable, read-only, asynchronous, radiationhardened, 32K x 8 memory - Supported by industry standard programmer q 65ns maximum address access time (-55 oC to +125 oC) q Three-state data bus q Low operating and standby current - Operating: 50.0
6	UT700	Aeroflex Circuit Technology	32-bit Fault-Tolerant SPARC V8/LEON 3FT Processor  Supports up to 166 MHz clock rate  Separate instruction and data cache architecture  High-performance fully pipelined IEEE-754 FPU  Enhanced pipeline with 1.2 DMIPS / MHz performance  Implemented on 130nm CMOS technology  Internally configured
7	UT54ACTS899	Aeroflex Circuit Technology	9-bit Latchable Transceiver  Latchable transceiver with output source/sink of 24mA  Option to select generate parity and check or "feed-through" data/parity in directions A-to-B or B-to-A  Independent latch enable for A-to-B and B-to-A directions  Select pin for ODD/EVEN pa
8	UT54ACTS245E	Aeroflex Circuit Technology	Octal Bus Transceiver  Three-state outputs drive bus line directly  m CRH CMOS process - Latchup immune  High speed  Low power consumption  Wide power supply operating range of 3.0V to 5.5V  Available QML Q or V processes Flexible package  - 20-lead flatpa
9	ACT7005	Aeroflex Circuit Technology	ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ Subsystem • Incorporates Transceivers, Protocol, and System Interface Components into a Single Hybrid Package • Functions as a Remote Terminal or Bus Controller • Interfaces to µP as a Simple Peripheral Unit CIRCUIT TECHNOLOGY www.aeroflex.com • +5V Operation
10	UT54ACTS109	Aeroflex Circuit Technology	Radiation-Hardened Dual J-K Flip-Flops • • • • • • radiation-hardened CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 16-pin DIP - 16-lead flatpack PINOUTS 16-Pin DIP Top View CLR1 J K1 CLK1 PRE1 Q1 Q1 VSS 1 2
11	UT54ACTS540	Aeroflex Circuit Technology	Octal Buffers & Line Drivers Three-state outputs drive bus lines or buffer memory address registers 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 20-pin DIP - 20-lead flatpack UT
12	UT8ER512K32	Aeroflex Circuit Technology	Monolithic 16M SRAM  20ns Read, 10ns Write maximum access times  Functionally compatible with traditional 512K x 32 SRAM devices  CMOS compatible input and output levels, three-state bidirectional data bus - I/O Voltage 3.3 volt, 1.8 volt core  Operational environme
13	UT01VS33D	Aeroflex Circuit Technology	Voltage Supervisor  3.15V to 3.6V Operating voltage range  Power supply (VDD) monitor set by the internal voltage reference at 3.08V  Precision Input Voltage Monitor using an internal 0.6V voltage reference  Watchdog Timer Circuit monitoring activity on WDI input -
14	UT54ACS08	Aeroflex Circuit Technology	Quadruple 2-Input AND Gates 1.2μ CMOS - Latchup immune High speed Low power consumption Single 5 volt supply Available QML Q or V processes Flexible package - 14-pin DIP - 14-lead flatpack UT54ACS08 - SMD 5962-96518 UT54ACTS08 - SMD 5962-96519 DESCRIPTION The U
15	UT54ACS132E	Aeroflex Circuit Technology	Quadruple 2-Input NAND Schmitt Triggers • 0.6μm CRH CMOS Process - Latchup immune • High speed • Low power consumption • Wide operating power supply from 3.0V to 5.5V • Available QML Q or V processes • 14-lead flatpack DESCRIPTION The UT54ACS132 is a quadruple 2-input NAND gate with Schmit
16	ACT7006	Aeroflex Circuit Technology	ACT7005/7006 Single Package Solution Dual Transceiver/ Protocol/ Subsystem
17	UTXQ512	Aeroflex Circuit Technology	CONVERTING AEROFLEX UTMC UT9Q512 4M SRAM into an SEU IMMUNE 1M X 1 SRAM pF or less. If the system loading is greater than 50 pF, the user should consult the “Operational Frequency vs. Load Capacitance” application note to calculate the true performance of the design. This application note can be downloaded from: http://w
18	UT54LVDS032	Aeroflex Circuit Technology	Quad Receiver q q q q q q q q >155.5 Mbps (77.7 MHz) switching rates +340mV differential signaling 5 V power supply TTL compatible outputs Ultra low power CMOS technology 8.0ns maximum propagation delay 3.0ns maximum differential skew Radiation-hardened design; to
19	54ACS164245S	Aeroflex Circuit Technology	UT54ACS164245S • Voltage translation - 5V bus to 3.3V bus www.DataSheet4U.com - 3.3V bus to 5V bus • Cold sparing - 1M Ω minimum input impedance power-off • 0.6µm Commercial CMOS - Total dose: 100K rad(Si) - Single Event Latchup immune • High speed, low power consu
20	UT8QNF8M8	Aeroflex Circuit Technology	64Mbit NOR Flash Memory  64Mbits organized as either 8M x 8-bits or 4M x16-bits  Fast 60ns read/write access time  Functionally compatible with traditional single power supply Flash devices  Simultaneous read/write operations  Flexible bank architecture  Single 3.3V p