| No. | Partie # | Fabricant | Description | Fiche Technique |
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ATMEL Corporation |
Rad Hard 512K x 8 Very Low Power CMOS SRAM • Operating Voltage: 3.3V • Access Time: • • • • • • • • • • – 15 ns (Preview) for 3.3V biased only (AT60142E) – 17 ns and 20 ns for 5V Tolerant (AT60142ET) Very Low Power Consumption – Active: 810 mW (Max) @ 15 ns – Standby: 215 µW (Typ) Wide Temper |
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ATMEL Corporation |
Rad Hard 512K x 8 Very Low Power CMOS SRAM • Operating Voltage: 3.3V • Access Time: • • • • • • • • • • – 15 ns (Preview) for 3.3V biased only (AT60142E) – 17 ns and 20 ns for 5V Tolerant (AT60142ET) Very Low Power Consumption – Active: 810 mW (Max) @ 15 ns – Standby: 215 µW (Typ) Wide Temper |
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ATMEL |
Coprocessor Field Programmable Gate Arrays • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfiguration |
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ATMEL Corporation |
Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module • • • • • • • • • • • • • • • 16 www.DataSheet4U.com Mbit SRAM Multi Chip Module Allows 32-, 16- or 8-bit access configuration Operating Voltage: 3.3V + 0.3V Access Time – 20 ns, 18 ns for AT68166F – <18 ns for AT68166G (in development prototypes in |
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ATMEL Corporation |
Rad Hard 16 MegaBit 3.3V 5V Tolerant SRAM Mult • • • • • • • • • • • • • • • 16 www.DataSheet4U.com Mbit SRAM Multi Chip Module Allows 32-, 16- or 8-bit access configuration Operating Voltage: 3.3V + 0.3V, 5V Tolerant Access Time: – 25 ns, 20 ns – 18 ns (preliminary information) Very Low Power Co |
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ATMEL Corporation |
Space FPGA Configuration Memory www.DataSheet4U.com • 4Mbits x1 Non Volatile Memory Designed to Store Field Programmable Gate • • • • • • • • • • • • • • • Arrays (FPGAs) Configurations In-System Programming (ISP) via Two-Wire Bus Simple Interface to SRAM FPGAs Compatible wit |
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ATMEL |
Coprocessor Field Programmable Gate Arrays • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfiguration |
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ATMEL |
Coprocessor Field Programmable Gate Arrays • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfiguration |
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ATMEL |
Coprocessor Field Programmable Gate Arrays • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfiguration |
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ATMEL |
Coprocessor Field Programmable Gate Arrays • High-performance – System Speeds > 100 MHz – Flip-flop Toggle Rates > 250 MHz – 1.2 ns/1.5 ns Input Delay – 3.0 ns/6.0 ns Output Delay • Up to 204 User I/Os • Up to 6,400 Registers • Cache Logic® Design – Complete/Partial In-System Reconfiguration |
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ATMEL Corporation |
Rad Hard 2-Mbit x 8 SRAM Cube • • • • • • • • • • • www.DataSheet4U.com Organized as 2M x 8 bits Single 3.3V Power Supply Stacks of 16 SRAM 128K x AT65609E Die Access Time: 40 ns read, 35 ns write Very Low Power Consumption – Active: 130 mW (Typ) – Standby: 1 mW (Typ) TTL-Compati |
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ATMEL Corporation |
Rad Hard 16 MegaBit 3.3V SRAM MultiChip Module • • • • • • • • • • • • • • • 16 www.DataSheet4U.com Mbit SRAM Multi Chip Module Allows 32-, 16- or 8-bit access configuration Operating Voltage: 3.3V + 0.3V Access Time – 20 ns, 18 ns for AT68166F – <18 ns for AT68166G (in development prototypes in |
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ATMEL Corporation |
Rad-Hard 32 bit SPARC V8 Processor www.DataSheet4U.com • SPARC V8 High Performance Low-power 32-bit Architecture • • • • • • • • • • • • • – LEON2-FT 1.0.13 compliant – 8 Register Windows Advanced Architecture: – On-chip Amba Bus – 5 Stage Pipeline – 16 kbyte Multi-sets Data C |
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