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The XCR3064XL is a 3.3V, 64-macrocell CPLD targeted at power sensitive designs that require leading edge programmable logic solutions. A total of four function blocks provide 1,500 usable gates. Pin-to-pin propagation delays are 6.0 ns with a maximum system frequency of 145 MHz. TotalCMOS Design Technique for Fast Zero Power Xilinx offers a TotalCMOS CPLD, .
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• Lowest power 64 macrocell CPLD 6.0 ns pin-to-pin logic delays System frequencies up to 145 MHz 64 macrocells with 1,500 usable gates Available in small footprint packages
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• 44-pin PLCC (36 user I/O pins) 44-pin VQFP (36 user I/O pins) 48-ball CS BGA (40 user I/O pins) 56-ball CP BGA (48 user I/O pins) 100-pin VQFP (68 user I/O pins) Ultra-low power operation 5V tolerant I/O pins with 3.3V core supply Advanced 0.35 micron five layer metal EEPROM process Fast Zero Power™ (FZP) CMOS design technology In-system programming Predictable timing model Up to 23 available clocks per function.
| No. | Partie # | Fabricant | Description | Fiche Technique |
|---|---|---|---|---|
| 1 | XCR3064XL-7PC44C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
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| 2 | XCR3064XL-7CP56C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 3 | XCR3064XL-7CP56I |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 4 | XCR3064XL-7CS48C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 5 | XCR3064XL-7CS48I |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 6 | XCR3064XL-7VQ100C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 7 | XCR3064XL-7VQ100I |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 8 | XCR3064XL-7VQ44C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 9 | XCR3064XL-7VQ44I |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
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| 10 | XCR3064XL-10CP56C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
|
| 11 | XCR3064XL-10CP56I |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
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| 12 | XCR3064XL-10CS48C |
Xilinx |
XCR3064XL 64 Macrocell CPLD |
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