The internal timer counting is based on an 8Mhz clock input from X1, X2 ( or X2, with X1 connected to ground). After the deassertion of RESET#, the VT82C42 will drive high at pin P23 and pin P27. After 6 µs (6 x 8 clocks) of driving, the VT82C42 will check on pins T1 & P10; if both pins are low, then the VT82C42 will switch to PS/2 mode. Otherwise, the VT82.
∗ ∗ ∗ ∗ ∗ Fully hardware implemented, 0.8µm CMOS Technology. Very high speed response of A20 GATE & reset. Support PS2 style mouse. Compatible with all major BIOS, including AWARD, PHOENIX and AMI. 40 pin PDIP and 44 pin PLCC packages. 3. Function Description: The internal timer counting is based on an 8Mhz clock input from X1, X2 ( or X2, with X1 connected to ground). After the deassertion of RESET#, the VT82C42 will drive high at pin P23 and pin P27. After 6 µs (6 x 8 clocks) of driving, the VT82C42 will check on pins T1 & P10; if both pins are low, then the VT82C42 will switch to PS/2 mo.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | VT82C570M |
VIA |
Green Pentium/P54C PCI/ISA System | |
2 | VT82C580VPX |
VIA |
OCI North Bridge | |
3 | VT82C586A |
ETC |
PIC Integrated Peripheral Controller | |
4 | VT82C586B |
ETC |
PCI INTEGRATED PERIPHERAL CONTROLLER | |
5 | VT82C596 |
ETC |
MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER | |
6 | VT82C596 |
ETC |
PCI INTEGRATED PERIPHERAL CONTROLLER | |
7 | VT82C596A |
ETC |
MOBILE PCI INTEGRATED PERIPHERAL CONTROLLER | |
8 | VT82C596B |
ETC |
PCI INTEGRATED PERIPHERAL CONTROLLER | |
9 | VT82C686A |
ETC |
PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER | |
10 | VT82C686A |
VIA |
PCI SUPER-I/O INTEGRATED PERIPHERAL CONTROLLER | |
11 | VT82C686B |
VIA |
Super South / South Bridge | |
12 | VT82C691 |
VIA Technologies |
Apollo Pro 66/100 MHZ Single-chip Socket-8/slot-1 North Bridge |