V54C3256804VT - Mosel Vitelic Corp

V54C3256804VT 256Mbit SDRAM 3.3 VOLT/ TSOP II / SOC BGA / WBGA PACKAGE 16M X 16/ 32M X 8/ 64M X 4

The V54C3256(16/80/40)4V(T/S/B) is a four bank Synchronous DRAM organized as 4 banks x 4Mbit x 16, 4 banks x 8Mbit x 8, or 4 banks x 16Mbit x 4. The V54C3256(16/80/40)4V(T/S/B) achieves high speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock All of the.

Features

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■ 4 banks x 4Mbit x 16 organization 4 banks x 8Mbit x 8 organization 4 banks x16Mbit x 4 organization High speed data transfer rates up to 166 MHz Full Synchronous Dynamic RAM, with all signals referenced to clock rising edge Single Pulsed RAS Interface Data Mask for Read/Write Control Four Banks controlled by BA0 & BA1 Programmable CAS Latency: 2, 3 Programmable Wrap Sequence: Sequential or Interleave Programmable Burst Length: 1, 2, 4, 8 for Sequential Type 1, 2, 4, 8 for Interleave Type Multiple Burst Read with Single Write Operation Automatic and Controlled Precharge Co.