UT54ACS109E - Aeroflex Circuit Technology

UT54ACS109E Dual J-K Flip-Flops

The UT54ACS109E is a dual J-K positive triggered flip-flop. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following .

Features

• 0.6μm CRH CMOS Process - Latchup immune
• High speed
• Low power consumption
• Wide operating power supply of 3.0V to 5.5V
• Available QML Q or V processes
• 16-lead flatpack DESCRIPTION The UT54ACS109E is a dual J-K positive triggered flip-flop. A low level at the preset or clear inputs sets or resets the outputs regardless of the other input levels. When preset and clear are inactive (high), data at the J and K input meeting the setup time requirements are transferred to the outputs on the positive-going edge of the clock pulse. Following the hold time interval, data at the J and K input c.