UR5595 - UTC

UR5595 DDR TERMINATION REGULATOR

The UTC UR5595 is a linear bus termination regulator designed to meet JEDEC SSTL-2 and SSTL-3 (Stub Series Terminated Logic) specifications for termination of DDR-SDRAM. The device contains a high-speed operational amplifier to provide excellent response to the load transients, and can deliver 1.5A continuous current and transient peaks up to 3A in the appl.

Features

* Power regulating with driving and sinking capability
* Low output voltage offset
* No external resistors required
* Low external component count
* Linear topology
* Low cost and easy to use
* Thermal shutdown protection
 ORDERING INFORMATION Ordering Number UR5595G-S08-R UR5595G-SH2-R Package SOP-8 HSOP-8 Packing Tape Reel Tape Reel www.unisonic.com.tw Copyright © 2015 Unisonic Technologies Co., Ltd 1 of 11 QW-R502-062.C UR5595
 MARKING
 PIN CONFIGURATION CMOS IC
 PIN DESCRIPTION PIN NO 1 2 3 4 5 6 7 8 PIN NAME NC GND VSENSE VREF VDDQ AVIN PVIN VTT DESCRIPTION No internal co.