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UM6104 - UMC

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UM6104 1K x 4 CMOS SRAM

The UM6104 is a 1024x4 fu IIy stat ic CMOS. RAM. The device utilizes synchronous circuitry to achieve performance and low power operation. Pin Configuration Block Diagram On chip latches are provided for the addresses allowing efficient interfacing with microprocessor systems. The data output can be forced to a high impedance state for use in expanded me.

Features


• Single + 5V power supply
• Low power standby
• Low power operation
• Fast Access time . , 120/150/200/250 ns max.
• Data retention . . . . . . . . . . . . . . . . . . .. 2.0V min.
• Three-state outputs
• On-chip address register
• Synchronous circuitry
• Standard 18 pin DIP package
• TTL compatible input/output General Description The UM6104 is a 1024x4 fu IIy stat ic CMOS. RAM. The device utilizes synchronous circuitry to achieve performance and low power operation. Pin Configuration Block Diagram On chip latches are provided for the addresses allowing efficient interfacing wi.

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