UM10430 - NXP Semiconductors

UM10430 LPC18xx ARM Cortex-M3 microcontroller

2.8 Modifications: 20151210 LPC18xx user manual • Fixed formatting issues. • Added CREG1 register. See Table 90 “CREG1 register (CREG1, address 0x4004 3008) bit description”. • Updated text in Section 12.2.1 “Configuring the BASE_M3_CLK for high operating frequencies”: To ramp up the clock frequency to an operating frequency above 110 MHz configure the c.

Features

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• Added the line to the remark in Section 10.4.10 “USB0 frame length adjust register” and Section 10.4.11 “USB1 frame length adjust register”: This register should be read before the initialization of USB0 and USB1.
• Fixed typographical error in Section 6.2 “Features”: Cipher-Block chaining.
• Added the paragraph: The Motor control PWM is not available on LPC1810FET100, LPC1820FET100, and LPC1830FET100 parts to Section 31.1 “How to read this chapter”.
• Added 0x10 to all the offsets for exception numbers 53 and above ending with 0x110 for the QEI vector. See Table 72 “Connection of interrup.