TP33N10E - Motorola

TP33N10E MTP33N10E

www.DataSheet4U.com SEMICONDUCTOR TECHNICAL DATA MOTOROLA Order this document by MTP33N10E/D Designer's TMOS E-FET .™ Power Field Effect Transistor N–Channel Enhancement–Mode Silicon Gate This advanced TMOS E–FET is designed to withstand high energy in the avalanche and commutation modes. The new energy efficient design also offers a drain–to–source diod.

Features

RES 100 VOLTS RDS(on) = 0.06 OHM ® D G S CASE 221A
  –06, Style 5 TO
  –220AB MAXIMUM RATINGS (TC = 25°C unless otherwise noted) Rating Drain
  –Source Voltage Drain
  –Gate Voltage (RGS = 1.0 MΩ) Gate
  –Source — Continuous — Non
  –Repetitive (tp ≤ 10 ms) Drain Voltage — Continuous — Continuous @ 100°C — Single Pulse (tp ≤ 10 µs) Total Power Dissipation Derate above 25°C Operating and Storage Temperature Range Single Pulse Drain
  –to
  –Source Avalanche Energy — Starting TJ = 25°C (VDD = 25 Vdc, VGS = 10 Vdc, IL = 33 Apk, L = 1.000 mH, RG = 25 Ω) Thermal Resistance — Junction to Case — Junction to Ambient Maxi.