TC74AC112P/F TOSHIBA CMOS Digital Integrated Circuit Silicon Monolithic TC74AC112P, TC74AC112F Dual J-K Flip Flop with Preset and Clear The TC74AC112 is an advanced high speed CMOS DUAL J-K FLIP FLOP fabricated with silicon gate and double-layer metal wiring C2MOS technology. It achieves the high speed operation similar to equivalent Bipolar Schottky TTL wh.
• High speed: fmax = 170 MHz (typ.) at VCC = 5 V
• Low power dissipation: ICC = 4 μA (max) at Ta = 25°C
• High noise immunity: VNIH = VNIL = 28% VCC (min)
• Symmetrical output impedance: |IOH| = IOL = 24 mA (min)
Capability of driving 50 Ω transmission lines.
• Balanced propagation delays: tpLH ∼− tpHL
• Wide operating voltage range: VCC (opr) = 2 to 5.5 V
• Pin and function compatible with 74F112
Pin Assignment
TC74AC112P TC74AC112F
Weight DIP16-P-300-2.54A SOP16-P-300-1.27A
: 1.00 g (typ.) : 0.18 g (typ.)
Start of commercial production
1987-05
1
2014-03-01
IEC Logic Symbol
TC74AC112P.
No. | Partie # | Fabricant | Description | Fiche Technique |
---|---|---|---|---|
1 | TC74AC112F |
Toshiba Semiconductor |
Dual J-K Flip-Flop | |
2 | TC74AC112FN |
Toshiba Semiconductor |
Dual J-K Flip-Flop | |
3 | TC74AC11F |
Toshiba Semiconductor |
Triple 3-Input AND Gate | |
4 | TC74AC11FN |
Toshiba Semiconductor |
Triple 3-Input AND Gate | |
5 | TC74AC11P |
Toshiba Semiconductor |
Triple 3-Input AND Gate | |
6 | TC74AC109F |
Toshiba |
Dual J-K Flip-Flop | |
7 | TC74AC109P |
Toshiba |
Dual J-K Flip-Flop | |
8 | TC74AC10F |
Toshiba Semiconductor |
Triple 3-Input NAND Gate | |
9 | TC74AC10FN |
Toshiba Semiconductor |
Triple 3-Input NAND Gate | |
10 | TC74AC10P |
Toshiba Semiconductor |
Triple 3-Input NAND Gate | |
11 | TC74AC125F |
Toshiba Semiconductor |
Quad Bus Buffer | |
12 | TC74AC125FN |
Toshiba |
Quad Bus Buffer |